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PDF FM28V020 Data sheet ( Hoja de datos )
| Número de pieza | FM28V020 | |
| Descripción | 256Kbit Ferroelectric Nonvolatile RAM | |
| Fabricantes | Ramtron Corporation | |
| Logotipo |  |
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Preliminary
www.DataSheet4U.com
FM28V020
256Kbit Bytewide F-RAM Memory
Features
256Kbit Ferroelectric Nonvolatile RAM
• Organized as 32Kx8
• 1014 Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 40MHz
• Advanced High-Reliability Ferroelectric Process
Superior to Battery-backed SRAM Modules
• No battery concerns
• Monolithic reliability
• True surface mount solution, no rework steps
• Superior for moisture, shock, and vibration
• Resistant to negative voltage undershoots
General Description
The FM28V020 is a 32K x 8 nonvolatile memory that
reads and writes like a standard SRAM. A
ferroelectric random access memory or F-RAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and virtually unlimited write
endurance make F-RAM superior to other types of
memory.
In-system operation of the FM28V020 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The F-RAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM28V020 ideal
for nonvolatile memory applications requiring
frequent or rapid writes in the form of an SRAM.
SRAM Replacement
• JEDEC 32Kx8 SRAM pinout
• 60 ns Access Time, 90 ns Cycle Time
Low Power Operation
• 2.0V – 3.6V Power Supply
• Standby Current 90 µA (typ)
• Active Current 7 mA (typ)
Industry Standard Configurations
• Industrial Temperature -40° C to +85° C
• 28-pin “Green”/RoHS SOIC (-SG)
Device specifications are guaranteed over the
industrial temperature range -40°C to +85°C.
Pin Configuration
Ordering Information
FM28V020-SG
28-pin “Green”/RoHS SOIC
FM28V020-SGTR 28-pin “Green”/RoHS SOIC,
Tape & Reel
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.0
Apr. 2009
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 13
1 page  
www.DataShoeneet4oUf.cthome chip enable signals to an inactive state. The
chip enable must remain inactive for at least the
FM28V020 - 32Kx8 FRAM
minimum precharge time tPC.
Endurance
The FM28V020 is capable of being accessed at least
1014 times – reads or writes. An F-RAM memory
operates with a read and restore mechanism.
Therefore, an endurance cycle is applied on a row
basis. The F-RAM architecture is based on an array
of rows and columns. Rows are defined by A14-A3
and column addresses by A2-A0. The array is
organized as 4K rows of 8-bytes each. The entire row
is internally accessed once whether a single byte or
all eight bytes are read or written. Each byte in the
row is counted only once in an endurance calculation.
The user may choose to write CPU instructions and
run them from a certain address space. The table
below shows endurance calculations for 256-byte
repeating loop, which includes a starting address, 7
page mode accesses, and a CE precharge. The
number of bus clocks needed to complete an 8-byte
transaction is 8+1 at lower bus speeds, but 9+2 at
33MHz due to initial read latency and an extra clock
to satisfy the device’s precharge timing constraint tPC.
The entire loop causes each byte to experience only
one endurance cycle. F-RAM read and write
endurance is virtually unlimited even at 33MHz
system bus clock rate.
Table 1. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop
Bus Freq Bus Cycle 256-byte Endurance Endurance Years to
(MHz) Time (ns) Transaction Cycles/sec. Cycles/year Reach 1014
Time (µs)
Cycles
33
30
10.56
94,690
2.98 x 1012
33.5
25
40
12.8
78,125
2.46 x 1012
40.6
10
100
28.8
34,720
1.09 x 1012
91.7
5
200
57.6
17,360
5.47 x 1011
182.8
Rev. 1.0
Apr. 2009
Page 5 of 13
5 Page 
FM28V020 - 32Kx8 FRAM
www.DataShWeert4itUe.cCoymcle Timing 3 (/CE low) Note: /OE is low only to show effect of /WE on DQ pins
A(14:0)
WE
DQ(7:0)
tWC
tAWH
D out
tWZ
tWLA
tDS
D in
tWX
tDH
D out
D in
Page Mode Write Cycle Timing
Although sequential column addressing is shown, it is not required.
Power Cycle Timing
Rev. 1.0
Apr. 2009
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FM28V020.PDF ] | |
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