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PDF GS9090 Data sheet ( Hoja de datos )

Número de pieza GS9090
Descripción GenLINX-R III 270Mb/s Deserializer
Fabricantes Gennum Corporation 
Logotipo Gennum Corporation Logotipo



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No Preview Available ! GS9090 Hoja de datos, Descripción, Manual

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GS9090 GenLINX® III 270Mb/s
Deserializer for SDI and DVB-ASI
GS9090 Data Sheet
Key Features
• SMPTE 259M-C compliant descrambling and NRZI
to NRZ decoding (with bypass)
• DVB-ASI sync word detection and 8b/10b decoding
• Integrated line-based FIFO for data
alignment/delay, clock phase interchange, DVB-ASI
data packet extraction and clock rate interchange,
and ancillary data packet extraction
• Integrated VCO and reclocker
• Automatic or manual selection between SMPTE
video and DVB-ASI data
• Single serial digital input buffer with wide input
sensitivity
• User selectable additional processing features
including:
• TRS, ANC data checksum, and EDH CRC error
detection and correction
• programmable ANC data detection
• illegal code remapping
• Internal flywheel for noise immune H, V, F
extraction
• Automatic standards detection and indication
• Enhanced Gennum Serial Peripheral Interface
(GSPI)
• JTAG test interface
• Polarity insensitive for DVB-ASI and SMPTE
signals
• +1.8V core power supply with optional +1.8V or
+3.3V I/O power supply
• Small footprint (8mm x 8mm)
• Low power operation (typically 145mW)
• Pb-free and RoHS compliant
Applications
• SMPTE 259M-C Serial Digital Interfaces
• DVB-ASI Serial Digital Interfaces
Description
The GS9090 is a 270Mb/s reclocking deserializer with
an internal FIFO. When used in conjunction with one of
Gennum’s SDI Cable Equalizers, a receive solution for
SD-SDI and DVB-ASI applications can be realized.
In addition to reclocking and deserializing the input data
stream, the GS9090 performs NRZI-to-NRZ decoding,
descrambling as per SMPTE 259M-C, and word
alignment when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will word align
the data to K28.5 sync characters and 8b/10b decode
the received stream.
The integrated reclocker features a very wide Input
Jitter Tolerance, and is fully compatible with both
SMPTE and DVB-ASI input streams.
The GS9090 includes a range of data processing
functions such as error detection and correction,
automatic standards detection, and EDH support. The
device can also detect and extract SMPTE 352M
payload identifier packets and independently identify
the received video standard. This information is read
from internal registers via the host interface port.
TRS errors, EDH CRC errors, and ancillary data
checksum errors can all be detected and corrected. A
single DATA_ERROR pin is provided which is an
inverted logical 'OR'ing of all detectable errors.
Individual error status is stored in internal
‘ERROR_STATUS’ registers.
The GS9090 also incorporates a video line-based FIFO.
This FIFO may be used in four user-selectable modes
to carry out tasks such as data alignment / delay, clock
phase interchange, MPEG packet extraction and clock
rate interchange, and ancillary data packet extraction.
Parallel data outputs are provided in 10-bit multiplexed
format, with the associated parallel clock output signal
operating at 27MHz.
The GS9090 is Pb-free, and the encapsulation
compound does not contain halogenated flame
retardant (RoHS compliant).
28201 - 1 July 2005
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1. Pin Out
1.1 Pin Assignment
GS9090 Data Sheet
LF- 1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 IO_GND
PLL_GND
2
41 DOUT9
PLL_VDD 3
40 DOUT8
BUFF_VDD
4
DDI 5
DDI 6
BUFF_GND
7
TERM
8
NC 9
VBG
10
NC 11
GS9090
XXXXE3
YYWW
GENNUM
39 DOUT7
38 DOUT6
37 DOUT5
36 DOUT4
35 DOUT3
34 DOUT2
33 DOUT1
32 DOUT0
IOPROC_EN 12
31 RD_RESET
JTAG/HOST
13
30 RD_CLK
RESET
14
15
16
17 18
19 20 21 22
23 24
29
25 26 27 28
IO_VDD
Center Pad
(bottom of package)
Figure 1-1: Pin Assignment
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GS9090 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
51
Name
FW_EN
52 FIFO_EN
53 VCO_VDD
54 LB_CONT
55 VCO_GND
56 LF+
– Center Pad
Timing
Type Description
Non Input
Synchronous
Non Input
Synchronous
Analog
Analog
Analog
Analog
Input
Power
Input
Input
Power
Input
Power
CONTOL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to enable or disable the noise immune flywheel of the device.
When set HIGH, the internal flywheel is enabled. This flywheel is used
in the extraction of timing signals, the generation of TRS signals, the
automatic detection of video standards, and in manual switch line lock
handling.
When set LOW, the internal flywheel is disabled. Timing based TRS
errors will not be detected.
CONTOL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to enable / disable the internal FIFO.
When FIFO_EN is HIGH, the internal FIFO will be enabled. Data will be
clocked out of the device on the rising edge of the RD_CLK input pin if
the FIFO is in video mode or DVB-ASI mode.
When FIFO_EN is LOW, the internal FIFO is bypassed and parallel
data is clocked out on the rising edge of the PCLK output.
Power supply connection for Voltage-Controlled-Oscillator. Connect to
+1.8V DC.
CONTROL SIGNAL INPUT
Control voltage to fine-tune the loop bandwidth of the PLL.
Ground connection for Voltage-Controlled-Oscillator. Connect to GND.
Loop filter component connection. Connect to pin 1 (LF-) as shown in
the Typical Application Circuit (Part B) on page 67.
Connect to GND following the Recommended PCB Footprint on
page 69
28201 - 1 July 2005
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