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PDF KK4040B Data sheet ( Hoja de datos )
| Número de pieza | KK4040B | |
| Descripción | 12-Stage Binary Ripple Counter High-Voltage Silicon-Gate CMOS | |
| Fabricantes | KODENSHI KOREA | |
| Logotipo |  |
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TECHNICAL DATA
KK4040B
12-Stage Binary Ripple Counter
High-Voltage Silicon-Gate CMOS
The KK4040B is ripple-carry binary counter. All counter stages are master-
slave flip-flops. The state of a counter advances one count on the negative
transition of each input pulse; a high level on the RESET line resets the counter
to its all zeros state. Schmitt trigger action on the input-pulse line permits
unlimited rise and fall times.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
N SUFFIX
PLASTIC DIP
16
1
16
1
ORDERING INFORMATION
KK4040BN Plastic DIP
KK4040BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
CLOCK 10
9
Q1
7
Q2
6
Q3
5 Q4
3
Q5
2
Q6
4 Q7
13 Q8
12
Q9
14 Q10
15
Q11
1
Q12
11
RESET
PIN 16 =VCC
PIN 8 = GND
PIN ASSIGNMENT
Q12 1
Q6 2
Q5 3
Q7 4
Q4 5
Q3 6
Q2 7
GND 8
16 VCC
15 Q11
14 Q10
13 Q8
12 Q9
11 RESET
10 CLOCK
9 Q1
FUNCTION TABLE
Inputs
Clock Reset
L
L
XH
H= high level
L = low level
X=don’t care
Output
Output state
No change
Advance to next
state
All Outputs are low
1
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CLOCK
RESET
ANY Q
tw
50%
t PHL
50%
50%
trem
Figure 3. Switching Waveforms
VCC
GND
VCC
GND
VCC
GND
KK4040B
Clock
Reset
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
TIMING DIAGRAM
012 4
8 16 32 64 128 256 512 1024 2048 4096
EXPANDED LOGIC DIAGRAM
CLOCK
RESET
CL1 Q1
FF1
CL1 Q1
R Q1
CL2 Q2
FF2
CL2 Q2
R
CL3 Q11
CL3 Q11
FF3-FF11
CL7 Q12
FFI2
CL7 Q12
R
Q1 Q2 Q3 Q11
Q12
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet KK4040B.PDF ] | |
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