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PDF KK4027B Data sheet ( Hoja de datos )
| Número de pieza | KK4027B | |
| Descripción | Dual JK Flip-Flop | |
| Fabricantes | KODENSHI KOREA | |
| Logotipo |  |
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Dual JK Flip-Flop
TECHNICAL DATA
KK4027B
The KK4027B is a Dual JK Flip-Flop which is edge-triggered and
features independent Set, Reset, and Clock inputs. Data is accepted when
the Clock is LOW and transferred to the output on the positive-going edge
of the Clock. The active HIGH asynchronous Reset and Set are
independent and override the J, K, or Clock inputs. The outputs are
buffered for best system performance.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4027BN Plastic
KK4027BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16 =VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Qn+1 Qn+1
L H X XX L H
H L X XX H L
H H X XX H H
LL
L L No change
LL
HL H L
LL
LH L H
LL
H H Qn Qn
X = don’t care
Qn+1 = State After Clock Positive Transition
1
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K(J)
CLOCK
Q(Q)
SET
(RESET)
0.5
tSU
0.9
0.5
0.1
tLH
tW
0.9
0.5
0.1
tHL
tREM
tPHL(tPLH)
0.5VCC
0.5
ÂSûõEîTä nQ(nQ)
(RESET)
RESET
(SET)
Q(Q)
0.5
tW2
0.9
0.5VCC
0.1
tTHL(tTLH)
tPHL(tPLH)
Figure 1. Switching Waveforms
KK4027B
VCC
0V
VCC
0V
VOHCC
VOL
VCC
0V
VCC
0V
VCC
0V
UUVODOLHDCC
0V
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet KK4027B.PDF ] | |
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