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Número de pieza IBM0418A81BLAB
Descripción (IBM04xxAx1BLAB) 8Mb and 4Mb SRAM
Fabricantes IBM Corporation 
Logotipo IBM Corporation Logotipo



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Preliminary
.
IBM0418A81BLAB IBM0436A81BLAB
IBM0418A41BLAB IBM0436A41BLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
• 8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
• 0.25 Micron CMOS technology
• Synchronous Pipeline Mode of Operation with
Self-Timed Late Write
• Single Differential HSTL Clock
• +2.5V Power Supply, Ground, 1.5, 1.8V VDDQ,
and 0.90V VREF
• HSTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
• Registered Outputs
• Common I/O
• Asynchronous Output Enable
• Synchronous Power Down Input
• Boundary Scan using limited set of JTAG
1149.1 functions
• Byte Write Capability and Global Write Enable
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
The 4Mb and 8Mb SRAMs—IBM0436A41BLAB,
IBM0418A41BLAB, IBM0418A81BLAB, and
IBM0436A81BLAB—are Synchronous Pipeline
Mode, high-performance CMOS Static Random
Access Memories that are versatile, wide I/O, and
can achieve 3ns cycle times. Differential K clocks
are used to initiate the read/write operation and all
internal operations are self-timed. At the rising edge
of the K clock, all Addresses, Write-Enables, Sync
Select, and Data Ins are registered internally. Data
Outs are updated from output registers off the next
rising edge of the K clock. An internal Write buffer
allows write data to follow one cycle after addresses
and controls. The device is operated with a single
+2.5V power supply and is compatible with HSTL
I/O interfaces.
crrh2519.07
12/13/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 25

1 page




IBM0418A81BLAB pdf
www.DataSheet4U.com
Preliminary
IBM0418A81BLAB IBM0436A81BLAB
IBM0418A41BLAB IBM0436A41BLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
SRAM Features
Late Write
Late Write function allows for write data to be registered one cycle after addresses and controls. This feature
eliminates one bus-turnaround cycle, necessary when going from a Read to a Write operation. Late Write is
accomplished by buffering write addresses and data so that the write operation occurs during the next write
cycle. When a read cycle occurs after a write cycle, the address and write data information are stored tempo-
rarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be
updated with address and data from the holding registers. Read cycle addresses are monitored to determine
if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array
occurs on a byte-by-byte basis. When only one byte is written during a write cycle, read data from the last
written address will have new byte data from the write buffer and remaining bytes from the SRAM array.
Mode Control
Mode control pins M1 and M2 are used to select four different JEDEC-standard read protocols. This SRAM
supports Single Clock, Pipeline (M1 = VSS, M2 = VDD). This datasheet only describes Single Clock Pipeline
functionality. Mode control inputs must be set with power up and must not change during SRAM operation.
This SRAM is tested only in the Pipeline mode.
Sleep Mode
Sleep Mode is enabled by switching synchronous signal ZZ High. When the SRAM is in Sleep mode, the out-
puts will go to a High-Z state and the SRAM will draw standby current. SRAM data will be preserved and a
recovery time (tZZR) is required before the SRAM resumes normal operation.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow for the
SRAM to adjust its output driver impedance. The value of RQ must be tbdX the value of the intended line
impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching is between
175and 350, with the tolerance described in Programmable Impedance Output Driver DC Electrical Char-
acteristics on page 9. The RQ resistor should be placed less than two inches away from the ZQ ball on the
SRAM module. The total external capacitance (including wiring ) seen by the ZQ ball should be minimized
(less than 7.5 pF).
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. One evaluation occurs every 64 clock cycles and each evaluation
may move the output driver impedance level only one step at a time towards the optimum level. The output
driver has 32 discrete binary weighted steps. The impedance update of the output driver occurs when the
SRAM is in High-Z. Write and Deselect operations will synchronously switch the SRAM into and out of High-
Z, therefore triggering an update. The user may choose to invoke asynchronous G updates by providing a G
setup and hold about the K clock to guarantee the proper update. There are no power-up requirements for
the SRAM; however, to guarantee optimum output driver impedance after power up, the SRAM needs 4096
clock cycles followed by a Low-Z to High-Z transition.
Power-Up and Power-Down Sequencing
The Power supplies need to be powered up in the following order: VDD, VDDQ, VREF, and Inputs. The power-
down sequencing must be the reverse. VDDQ can be allowed to exceed VDD by no more than 0.6V.
crrh2519.07
12/13/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 25

5 Page





IBM0418A81BLAB arduino
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Preliminary
IBM0418A81BLAB IBM0436A81BLAB
IBM0418A41BLAB IBM0436A41BLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
AC Characteristics (TA = 0 to +85°C, VDD = 2.5V -5%, +5%)
Parameter
3 3F 3N 4 5
Symbol
Units Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Cycle Time
Clock High Pulse Width
Clock Low Pulse Width
Clock to Output Valid
Address Setup Time
Address Hold Time
Sync Select Setup Time
Sync Select Hold Time
Write Enables Setup Time
Write Enables Hold Time
Data In Setup Time
Data In Hold Time
Data Out Hold Time
Clock High to Output High-Z
Clock High to Output Active
Output Enable to High-Z
Output Enable to Low-Z
Output Enable to Output Valid
Output Enable Setup Time
Output Enable Hold TIme
Sleep Mode Setup Time
Sleep Mode Hold Time
Sleep Mode Recovery TIme
Sleep Mode Enable TIme
tKHKH
tKHKL
tKLKH
tKHQV
tAVKH
tKHAX
tSVKH
tKHSX
tWVKH
tKHWX
tDVKH
tKHDX
tKHQX
tKHQZ
tKHQX4
tGHQZ
tGLQX
tGLQV
tGHKH
tKHGX
tZVKH
tKHZX
tZZR
tZZE
3.0
1.2
1.2
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1.5
1.0
1.0
200
— 3.3 — 3.7
— 1.5 — 1.5
— 1.5 — 1.5
1.7 — 1.8 —
— 0.5 — 0.5
— 0.5 — 0.5
— 0.5 — 0.5
— 0.5 — 0.5
— 0.5 — 0.5
— 0.5 — 0.5
— 0.5 — 0.5
— 0.5 — 0.5
— 0.5 — 0.5
2.25 — 2.25 —
— 0.5 — 0.5
2.0 2.0
— 0.5 — 0.5
2.0 — 2.0 —
— 0.5 — 0.5
— 1.5 — 1.5
— 1.0 — 1.0
— 1.0 — 1.0
— 200 — 200
6 — 6.6 —
— 4.0 — 5.0 —
— 1.5 — 1.5 —
— 1.5 — 1.5 —
1.8 — 2.0 — 2.25
— 0.5 — 0.5 —
— 0.5 — 1.0 —
— 0.5 — 0.5 —
— 0.5 — 1.0 —
— 0.5 — 0.5 —
— 0.5 — 1.0 —
— 0.5 — 0.5 —
— 0.5 — 1.0 —
— 0.5 — 0.5 —
2.25 — 2.25 — 2.5
— 0.5 — 0.5 —
2.0 2.0 — 2.5
— 0.5 — 0.5 —
2.0 — 2.0 — 2.5
— 0.5 — 0.5 —
— 1.5 — 1.5 —
— 1.0 — 1.0 —
— 1.0 — 1.0 —
— 200 — 200 —
7.4 — 8 — 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1, 2
1, 2
4
1. See the AC Test Loading figure on page 10.
2. Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce Output Driver
updates during High-Z.
3. During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of Clock.
4. For tZZR<200ns, access time will be equal to twice tKHQV.
crrh2519.07
12/13/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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