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PDF LF43881JC40 Data sheet ( Hoja de datos )
| Número de pieza | LF43881JC40 | |
| Descripción | 8 x 8-bit Digital Filter | |
| Fabricantes | LOGIC Devices Incorporated | |
| Logotipo |  |
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DEVICES INCORPORATED
DEVICES INCORPORATED
LF43881
8 x 8-LbiFt D4ig3it8al8Fi1lter
8 x 8-bit Digital Filter
FEATURES
DESCRIPTION
u 25 MHz Maximum Sampling Rate
u 320 MHz Multiply-Accumulate Rate
u 8 Filter Cells
u 8-bit Unsigned or Two’s Complement
Data
u 8-bit Unsigned or Two’s Complement
Coefficients
u 26-bit Data Outputs
u Shift-and-Add Output Stage for
Combining Filter Outputs
u Expandable Data Size, Coefficient
Size, and Filter Length
u User-Selectable 2:1, 3:1, or 4:1
Decimation
u Replaces Harris HSP43881
u 84-pin PLCC, J-Lead
The LF43881 is a video-speed digital
filter that contains eight filter cells
(taps) cascaded internally and a shift-
and-add output stage. An 8 x 8
multiplier, three decimation registers,
and a 26-bit accumulator are con-
tained in each filter cell. The output
stage of the LF43881 contains a 26-bit
accumulator which can add the
contents of any filter stage to the
output stage accumulator shifted right
by 8 bits. 8-bit unsigned or two’s
complement format for data and
coefficients can be independently
selected.
Expanded coefficients and word sizes
can be processed by cascading mul-
tiple LF43881s to implement larger
filter lengths without affecting the
sample rate. By reducing the sample
rate, a single LF43881 can process
larger filter lengths by using multiple
passes. The sampling rate can range
from 0 to 40 MHz. Over 1000 taps
may be processed without overflows
due to the architecture of the device.
The output sample rate can be re-
duced to one-half, one-third, or one-
fourth the input sample rate by using
the three decimation registers con-
tained in every filter cell. Matrix
multiplication, N x N spatial correla-
tions/convolutions, and other 2-D
operations for image processing can
also be achieved using these registers.
LF43881 BLOCK DIAGRAM
DIN7-0
8
DIENB, CIENB,
ERASE, DCM1-0
5
TCS
TCCI
CIN7-0
8
3
ADR2-0
FILTER
CELL 0 8
26
FILTER
CELL 1 8
26
FILTER
CELL 2 8
26
FILTER
CELL 3 8
26
FILTER
CELL 4 8
26
FILTER
CELL 5 8
26
FILTER
CELL 6 8
26
FILTER
CELL 7 8
TCCO
COUT7-0
COENB
26
SHADD
SENBL
SENBH
RESET
CLK
TO ALL CELLS
TO ALL REGISTERS
MUX
26
OUTPUT
STAGE
26
SUM25-0
1
Video Imaging Products
08/16/2000–LDS.43881-J
1 page  
DEVICES INCORPORATED
LF43881
8 x 8-bit Digital Filter
Controls
CIENB — Coefficient Input Enable
ADR2-0 — Cell Accumulator Select
TCS — Data Format Control
The TCS input determines the inter-
pretation of the input data. When
TCS is HIGH, two’s complement
arithmetic is used. When TCS is
LOW, unsigned arithmetic is used.
TCCI — Coefficient Input Format Control
The TCCI input determines the
interpretation of the coefficients.
When TCCI is HIGH, two’s comple-
ment arithmetic is used. When TCCI
is LOW, unsigned arithmetic is used.
The CIENB input enables the C and D
registers of every filter cell. While
CIENB is LOW, the C and appropriate
D registers are loaded with the
coefficient data on the rising edge of
CLK. While CIENB is HIGH, the
contents of the C and D registers are
held and the CLK signal is ignored.
By using CIENB in its active state,
coefficient data can be shifted from
cell to cell. CIENB must be low one
clock cycle prior to presenting the
coefficient data on the CIN7-0 input
since it is latched and delayed inter-
nally.
The ADR2-0 inputs select which cell’s
accumulator will available at the
SUM25-0 output or added to the
output stage accumulator. In both
cases, ADR2-0 is latched and delayed
by one clock cycle. If the same
address remains on the ADR2-0 inputs
for more than one clock cycle,
SUM25-0 will not change if the con-
tents of the accumulator changes.
Only the result from the first selection
of the cell (first clock cycle) by ADR2-0
will be available. ADR2-0 is also used
to select which accumulator to clear
when ERASE is LOW.
TCCO — Coefficient Output Format
The TCCO output shows the format of
the COUT7-0 coefficient output.
TCCO follows the TCCI input. When
cascading multiple LF43881s, the
TCCO output of one device should be
connected to the TCCI input of
another device. The COENB signal
enables TCCO.
DIENB — Data Input Enable
The DIENB input enables the X
register of every filter cell. While
DIENB is LOW, the X registers are
loaded with the data present at the
DIN7-0 inputs on the rising edge of
CLK. While DIENB is HIGH, all bits
of DIN7-0 are forced to zero and a
rising edge of CLK will load the X
register of every filter cell with all
zeros. DIENB must be low one clock
cycle prior to presenting the input
data on the DIN7-0 input since it is
latched and delayed internally.
COENB — Coefficient Output Enable
The COENB input enables the
COUT7-0 and TCCO outputs. When
COENB is LOW, the outputs are
enabled. When COENB is HIGH, the
outputs are placed in a high-imped-
ance state.
DCM1-0 — Decimation Control
The DCM1-0 inputs select the num-
ber of decimation registers to use
(Table 1). Coefficients are passed
from one cell to another at a rate
determined by DCM1-0. When no
decimation registers are selected,
the coefficients are passed from cell
to cell on every rising edge of CLK
(no decimation). When one decima-
tion register is selected, the coeffi-
cients are passed from cell to cell on
every other rising edge of CLK (2:1
decimation). When two decimation
registers are selected, the coeffi-
cients are passed from cell to cell on
every third rising edge of CLK (3:1
decimation) and so on. DCM1-0 is
latched and delayed internally.
SENBH — MSB Output Enable
When SENBH is LOW, SUM25-16 is
enabled. When SENBH is HIGH,
SUM25-16 is placed in a high-imped-
ance state.
SENBL — LSB Output Enable
When SENBL is LOW, SUM15-0 is
enabled. When SENBL is HIGH,
SUM15-0 is placed in a high-imped-
ance state.
RESET — Register Reset Control
When RESET is LOW, all registers are
cleared simultaneously except the cell
accumulators. RESET can be used
with ERASE to clear all cell accumula-
tors. RESET is latched and delayed
internally. Refer to Table 2.
ERASE — Accumulator Erase Control
When ERASE is LOW, the cell accu-
mulator specified by ADR2-0 is
cleared. When RESET is LOW in
conjunction with ERASE, all cell
accumulators are cleared. Refer to
Table 2.
Video Imaging Products
5 08/16/2000–LDS.43881-J
5 Page 
DEVICES INCORPORATED
LF43881
8 x 8-bit Digital Filter
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Speed
Ceramic Pin Grid Array
(G3)
0°C to +70°C — COMMERCIAL SCREENING
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Video Imaging Products
11 08/16/2000–LDS.43881-J
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet LF43881JC40.PDF ] | |
Hoja de datos destacado
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