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PDF BLF6G10LS-200R Data sheet ( Hoja de datos )
| Número de pieza | BLF6G10LS-200R | |
| Descripción | Power LDMOS transistor | |
| Fabricantes | NXP Semiconductors | |
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BLF6G10LS-200R
Power LDMOS transistor
Rev. 01 — 21 January 2008
Preliminary data sheet
1. Product profile
1.1 General description
200 W LDMOS power transistor for base station applications at frequencies from
800 MHz to 1000 MHz.
Table 1. Typical performance
Typical RF performance at Tcase = 25 °C in a class-AB production test circuit.
Mode of operation
f
VDS
PL(AV)
Gp
ηD
(MHz)
(V) (W)
(dB) (%)
2-carrier W-CDMA
869 to 894
28 40
20 27.5
ACPR
(dBc)
−40[1]
[1] Test signal: 3GPP; test model 1; 64 DPCH; PAR = 7.5 dB at 0.01 % probability on CCDF per carrier; carrier
spacing 5 MHz.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
1.2 Features
I Typical 2-carrier W-CDMA performance at frequencies of 869 MHz and 894 MHz, a
supply voltage of 28 V and an IDq of 1400 mA:
N Average output power = 40 W
N Power gain = 20 dB
N Efficiency = 27.5 %
N ACPR = −40 dBc
I Easy power control
I Integrated ESD protection
I Enhanced ruggedness
I High efficiency
I Excellent thermal stability
I Designed for broadband operation (800 MHz to 1000 MHz)
I Internally matched for ease of use
I Compliant to Directive 2002/95/EC, regarding restriction of hazardous substances
(RoHS)
1 page  
www.DNatXaSPheSete4Um.coicmonductors
7.4 2-carrier W-CDMA
22
Gp
(dB)
21
Gp
20
ηD
19
001aah521
40
ηD
(%)
30
20
10
BLF6G10LS-200R
Power LDMOS transistor
−35
IMD3,
ACPR
(dBc)
−40
−45
IMD3
ACPR
−50
001aah522
18
0
0
20 40 60
PL(AV) (W)
VDS = 28 V; IDq = 1400 mA; f = 881 MHz (±5 MHz);
carrier spacing 10 MHz.
Fig 4. 2-carrier W-CDMA power gain and drain
efficiency as functions of average load power;
typical values
−55
0
20 40 60
PL(AV) (W)
VDS = 28 V; IDq = 1400 mA; f = 881 MHz (±5 MHz);
carrier spacing 10 MHz.
Fig 5. 2-carrier W-CDMA adjacent channel power ratio
and third order intermodulation distortion as
functions of average load power; typical values
8. Test information
input
50 Ω
VGG
R1
C3
R2
C1
C2
The drawing is not to scale.
Fig 6. Test circuit for operation at 800 MHz
C7
C8
C11 C13 C17
R3
L1
C5
VDD
C16
output
50 Ω
C6
C9 C10 C12 C14 C18
C15
001aah523
BLF6G10LS-200R_1
Preliminary data sheet
Rev. 01 — 21 January 2008
© NXP B.V. 2008. All rights reserved.
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