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PDF PCF8534 Data sheet ( Hoja de datos )
| Número de pieza | PCF8534 | |
| Descripción | Universal LCD driver | |
| Fabricantes | NXP Semiconductors | |
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PCF8534
Universal LCD driver for low multiplex rates
Rev. 00.05 — 20 February 2007
Preliminary datasheet
1. General description
The PCF8534 is a peripheral device which interfaces to almost any Liquid Crystal Display
(LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed
LCD containing up to four backplanes and up to 60 segments and can easily be cascaded
for larger LCD applications. The PCF8534 is compatible with most
microprocessors / microcontrollers and communicates via a two-line bidirectional I2C-bus.
Communication overheads are minimized using a display RAM with auto-incremented
addressing, hardware subaddressing and display memory switching (static and duplex
drive modes).
2. Features
Single-chip LCD controller / driver
Selectable backplane drive
configuration: static or 2 / 3 / 4
backplane multiplexing
Selectable display bias configuration: Internal LCD bias generation with
static, 1⁄2 or 1⁄3
60 segment drives: up to thirty
voltage-follower buffers
60 x 4-bit RAM for display data storage
8-segment numeric characters; up to
sixteen 15-segment alphanumeric
characters; or any graphics of up to
240 elements
Auto-incremented display data loading Display memory bank switching in static
across device subaddress boundaries
and duplex drive modes
Versatile blinking modes
LCD and logic supplies may be
separated
Wide power supply range: from
Wide LCD supply range: from 2.5 V for
1.8 to 5.5 V
low threshold LCDs and up to 6.5 V for
guest-host LCDs and high threshold
(automobile) twisted nematic LCDs
Low power consumption
400 kHz I2C-bus interface
TTL/CMOS compatible
Compatible with 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers
May be cascaded for 2 LCD applications No external components
Manufactured in silicon gate CMOS
process.
1 page  
NXP Semiconductors
www.DataSheet4U.com
PCF8534
Universal LCD driver for low multiplex rates
Table 2.
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin allocation table …continued
Symbol
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
BP0
BP1
BP2
BP3
n.c.
n.c.
n.c.
n.c.
SDA
SCL
CLK
Pin
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Symbol
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
5.2 Pin description
Table 3.
Symbol
SDA
SCL
CLK
VDD
SYNC
Pin description
Pin
38
39
40
41
42
Description
I2C-bus serial data input / output
I2C-bus serial clock input
external clock input / output
supply voltage
cascade synchronization input / output
PCF8534_0
Preliminary datasheet
Rev. 00.05 — 20 February 2007
© NXP B.V. 2007. All rights reserved.
5 of 40
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NXP Semiconductors
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PCF8534
Universal LCD driver for low multiplex rates
BP0
BP1
Sn
Sn+1
state 1
state 2
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
0V
−VLCD/3
−2VLCD/3
−VLCD
VLCD
2VLCD/3
VLCD/3
0V
−VLCD/3
−2VLCD/3
−VLCD
Tframe
LCD segments
state 1
state 2
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
mgl747
Fig 6.
Vstate1(t) = Vsn(t) − VBP0(t).
VON(rms) = 0.745 VLCD.
Vstate2(t) = V(sn)(t) − VBP1(t).
VOFF(rms) = 0.333 VLCD.
Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias.
PCF8534_0
Preliminary datasheet
Rev. 00.05 — 20 February 2007
© NXP B.V. 2007. All rights reserved.
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