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PDF XR16M598 Data sheet ( Hoja de datos )
| Número de pieza | XR16M598 | |
| Descripción | 1.62V To 3.63V High Performance Octal UART | |
| Fabricantes | Sipex Corporation | |
| Logotipo |  |
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XR16M598
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
www.DataShMeAetY4U20.c0o8m
REV. 1.0.0
GENERAL DESCRIPTION
The XR16M5981 (598), is a 1.62V to 3.63V octal
Universal Asynchronous Receiver and Transmitter
(UART). The highly integrated device is designed for
high bandwidth requirement in communication
systems. The global interrupt source register
provides a complete interrupt status indication for all
8 channels to speed up interrupt parsing. Each UART
has its own 16C550 compatible set of configuration
registers, TX and RX FIFOs of 16 bytes, fully
programmable transmit and receive FIFO trigger
levels, automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis, automatic
software (Xon/Xoff) flow control, RS-485 half-duplex
direction control with programmable turn-around
delay, Intel or Motorola bus interface and sleep mode
with a wake-up indicator.
NOTE: Covered by US patents #5,649,122 and #5,949,787
APPLICATIONS
• Remote Access Servers
• Ethernet Network to Serial Ports
• Network Management
• Factory Automation and Process Control
• Point-of-Sale Systems
• Multi-port RS-232/RS-422/RS-485 Cards
FEATURES
• 1.62V to 3.63V supply voltage
• Single Interrupt output for all 8 UARTs
• A Global Interrupt Source Register for all 8 UARTs
• 5G “Flat” UART Registers for easier programming
• Simultaneous Initialization of all UART channels
• General Purpose 16-bit Timer/counter
• Sleep Mode with Wake-up Indication
• Highly Integrated Device for Space Saving
• Each UART is independently controlled with:
■ 16C550 Compatible 5G Register Set
■ 16-byte Transmit and Receive FIFOs
■ Fractional Baud Rate Generator
■ Programmable TX and RX FIFO Trigger Level
■ Automatic RTS/CTS or DTR/DSR Flow Control
■ Automatic Xon/Xoff Software Flow Control
■ RS-485 Half-Duplex Control Output with
Selectable Turn-around Delay
■ Infrared (IrDA 1.0) Data Encoder/Decoder
■ Programmable Data Rate with Prescaler
• Up to 15 Mbps Serial Data Rate
• Pin compatible to XR16V598, XR16V698,
XR16V798 and XR16M698
FIGURE 1. BLOCK DIAGRAM
RST#
A7:A0
D7:D0
IOR#
IOW#
CS#
INT#
16/68#
Data Bus
Interface
Device
Configuration
Registers
16-bit
Timer/Counter
UART Channel 0
UART
Regs
BRG
16 Byte TX FIFO
TX & RX
IR
ENDEC
16 Byte RX FIFO
UART Channel 1
UART Channel 2
UART Channel 3
UART Channel 4
UART Channel 5
UART Channel 6
UART Channel 7
Crystal Osc/Buffer
TX0, RX0, DTR0#,
DSR0#, RTS0#,
CTS0#, CD0#, RI0#
TX7, RX7, DTR7#,
DSR7#, RTS7#,
CTS7#, CD7#, RI7#
XTAL1
XTAL2
TMRCK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
www.DataShReEeVt4.U1..c0o.0m
NAME
RX4
PIN #
57
RTS4#
CTS4#
DTR4#
DSR4#
CD4#
RI4#
TX5
RX5
62
58
63
59
60
61
56
49
RTS5#
CTS5#
DTR5#
DSR5#
CD5#
RI5#
TX6
RX6
54
50
55
51
52
53
46
39
RTS6#
CTS6#
DTR6#
DSR6#
CD6#
RI6#
TX7
RX7
44
40
45
41
42
43
38
31
XR16M598
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
TYPE
DESCRIPTION
I UART channel 4 Receive Data or infrared receive data. Normal RXD input idles
HIGH. The infrared pulse can be inverted internally prior to decoding by setting
FCTR bit-4.
O UART channel 4 Request to Send or general purpose output (active LOW). See
description of RTS0# pin.
I UART channel 4 Clear to Send or general purpose input (active LOW). See descrip-
tion of CTS0# pin.
O UART channel 4 Data Terminal Ready or general purpose output (active LOW). See
description of DTR0# pin.
I UART channel 4 Data Set Ready or general purpose input (active LOW). See
description of DSR0# pin.
I UART channel 4 Carrier Detect or general purpose input (active LOW).
I UART channel 4 Ring Indicator or general purpose input (active LOW).
O UART channel 5 Transmit Data or infrared transmit data.
I UART channel 5 Receive Data or infrared receive data. Normal RXD input idles
HIGH. The infrared pulse can be inverted internally prior to decoding by setting
FCTR bit-4.
O UART channel 5 Request to Send or general purpose output (active LOW). See
description of RTS0# pin.
I UART channel 5 Clear to Send or general purpose input (active LOW). See descrip-
tion of CTS0# pin.
O UART channel 5 Data Terminal Ready or general purpose output (active LOW). See
description of DTR0# pin.
I UART channel 5 Data Set Ready or general purpose input (active LOW). See
description of DSR0# pin.
I UART channel 5 Carrier Detect or general purpose input (active LOW).
I UART channel 5 Ring Indicator or general purpose input (active LOW).
O UART channel 6 Transmit Data or infrared transmit data.
I UART channel 6 Receive Data or infrared receive data. Normal RXD input idles
HIGH. The infrared pulse can be inverted internally prior to decoding by setting
FCTR bit-4.
O UART channel 6 Request to Send or general purpose output (active LOW). See
description of RTS0# pin.
I UART channel 6 Clear to Send or general purpose input (active LOW). See descrip-
tion of CTS0# pin.
O UART channel 6 Data Terminal Ready or general purpose output (active LOW). See
description of DTR0# pin.
I UART channel 6 Data Set Ready or general purpose input (active LOW). See
description of DSR0# pin.
I UART channel 6 Carrier Detect or general purpose input (active LOW).
I UART channel 6 Ring Indicator or general purpose input (active LOW).
O UART channel 7 Transmit Data or infrared transmit data.
I UART channel 7 Receive Data or infrared receive data. Normal RXD input idles
HIGH. The infrared pulse can be inverted internally prior to decoding by setting
FCTR bit-4.
5
5 Page 
www.DataShReEeVt4.U1..c0o.0m
XR16M598
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
TABLE 5: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required
Output Data
Rate
400
2400
4800
9600
10000
19200
25000
28800
38400
50000
57600
75000
100000
115200
153600
200000
225000
230400
250000
300000
400000
460800
500000
750000
921600
1000000
DIVISOR FOR 16x
Clock
(Decimal)
DIVISOR
OBTAINABLE IN
598
DLM PROGRAM
VALUE (HEX)
3750
3750
E
625 625
2
312.5
312 8/16
1
156.25
156 4/16
0
150 150
0
78.125
78 2/16
0
60 60
0
52.0833
52 1/16
0
39.0625
39 1/16
0
30 30
0
26.0417
26 1/16
0
20 20
0
15 15
0
13.0208
13
0
9.7656
9 12/16
0
7.5 7 8/16
0
6.6667
6 11/16
0
6.5104
6 8/16
0
660
550
3.75 3 12/16
0
3.2552
3 4/16
0
330
220
1.6276
1 10/16
0
1.5 1 8/16
0
DLL PROGRAM DLD PROGRAM DATA ERROR
VALUE (HEX) VALUE (HEX)) RATE (%)
A6 0 0
71 0 0
38 8 0
9C 4 0
96 0 0
4E 2 0
3C 0 0
34 1 0.04
27 1 0
1E 0 0
1A 1 0.08
14 0 0
F 00
D 0 0.16
9 C 0.16
7 80
6 B 0.31
6 8 0.16
6 00
5 00
3 C0
3 4 0.16
3 00
2 00
1 A 0.16
1 80
2.7 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X or 8X or 4X (if
8X or 4X sampling is selected via the 8XMODE Register or 4XMODE Register) internal clock. A bit time is 16
(or 8 or 4) clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts the
proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line
Status Register (LSR bit-5 and bit-6).
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XR16M598.PDF ] | |
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