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Número de pieza | K6T2008S2M | |
Descripción | 256K X 8 Bit Low Power And Low Voltage CMOS Static RAM | |
Fabricantes | Samsung Semiconductor | |
Logotipo | ||
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Document Title
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0 Initial draft
1.0 Finalize
Draft Date
Remark
September 30, 1997 Preliminary
August 27, 1998
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 1.0
August 1998
1 page www.DataShKee6t4UT.c2om008S2M Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) : CL=100pF+1TTL
CL=30pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=2.3~2.7V, Commercial products:TA=0 to 70°C, Industrial products:TA=-40 to 85°C)
Parameter List
Read
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
1. The parameter is measured with 30pF test load.
Symbol
tRC
tAA
tCO1, tCO2
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW1, tCW2
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed Bins
120ns1)
150ns
Min Max Min Max
120 - 150 -
- 120 - 150
- 120 - 150
- 60 - 75
20 - 20 -
20 - 20 -
- 35 0 40
- 35 0 40
15 - 15 -
120 - 150 -
100 - 120 -
0-0-
100 - 120 -
80 - 100 -
0-0-
0 30 0 40
50 - 60 -
0-0-
5-5-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Vcc for data retention
Data retention current
VDR CS1≥Vcc-0.2V1)
IDR Vcc=2.0V, CS1≥Vcc-0.2V or CS2≤0.2V
Data retention set-up time
Recovery time
tSDR
tRDR
See data retention waveform
1. CS1≥ Vcc-0.2V, CS2≥Vcc-0.2V(CS1 Contrlled) or CS2≤0.2V(CS2 Controlled)
Min Typ Max Unit
2.0 - 3.3 V
- - 10 µA
0 - - ms
5- -
Revision 1.0
August 1998
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet K6T2008S2M.PDF ] |
Número de pieza | Descripción | Fabricantes |
K6T2008S2A | 256K X 8 Bit Low Power And Low Voltage CMOS Static RAM | Samsung Semiconductor |
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