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PDF IR3623MPBF Data sheet ( Hoja de datos )
| Número de pieza | IR3623MPBF | |
| Descripción | SINGLE OR DUAL OUTPUT SYNCHRONOUS STEP DOWN CONTROLLER | |
| Fabricantes | International Rectifier | |
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Data Sheet No.PD94717 revC
IR3623MPbF
HIGH FREQUENCY 2-PHASE, SINGLE OR DUAL OUTPUT SYNCHRONOUS STEP
DOWN CONTROLLER WITH OUTPUT TRACKING AND SEQUENCING
Features
Description
• Dual Synchronous Controller with 180o Out of Phase The IR3623 IC integrates a dual synchronous
Operation
Buck controller, along with IP2003A it is providing
• Configurable to 2-Independent Outputs or Current a high performance and flexible solution. The
Share Single Output
IR3623 can be configured as 2-independent
• Output Voltage Tracking
• Power up /down Sequencing
• Current Sharing Using Inductor’s DCR
outputs or as current share single output. The
current share configuration is ideal for high
current applications.
• +/-1% Accurate Reference Voltage
IR3623 enables output tracking and sequencing
• Programmable Switching Frequency up 1200kHz
• Programmable Over Current Protection
of multiple rails in either ratiometric or
simultaneous fashion. The IR3623 features 180o
• Hiccup Current Limit Using MOSFET RDS(on)
sensing
out of phase operation which reduces the
required input/output capacitance and results to
• Latched Overvoltage Protection
few number of capacitor quantity. The switching
• Dual Programmable Soft-Starts
frequency is programmable from 200kHz to
• Enable
• Pre-Bias Start-up
• Dual Power Good Outputs
• On Board Regulator
• External Frequency Synchronization
• Thermal Protection
• 32-Lead MLPQ Package
Applications
1200kHz per phase using one external resistor, in
addition IR3623 also allows the switching
frequency to be synchronized to an external clock
signal. Other key features offered by this device
include two independent programmable soft
starts, two independent power good outputs,
precision enable input and under voltage lockout
function. The current limit is provided by sensing
the lower MOSFET's on-resistance for optimum
• Embedded Telecom Systems
cost and performance. The output voltages are
• Distributed Point of Load Power Architectures
monitored through dedicated pins protect against
• Computing Peripheral Voltage Regulator
open circuit and enhance faster response to an
• Graphics Card
overvoltage event.
• General DC/DC Converters
12V
Vo1 Vo1
C1
Vout1
R10
R11
R1
C2 R2
C3 R3
OVP_Output
PGood1,2
C4
C5
5V_sns VOUT3
Vcc
Enable
Seq
Track1
Sync
Track2
Ph_En1
PWM1
VP1 OCSet1
VREF
VP2
IR3623
Vsns1
Rt Fb1
Fb2
Comp1
Vsns2
Comp2
OCSet2
OVP_Output
PGood1,2
SS1 / SD
SS2 / SD
SGnd
Ph_En2
PWM2
OCGnd
Gnd
C6
R4 SW1
Vsns1
Fb1
Fb2
Vsns2
R5 SW2
Vdd Vin
Enable1
IP2003A
PWM1
SW1
PRDY1
Gnd
PGnd
12V
Vdd Vin
PRDY2
Enable2
PWM2
SW2
PGnd IP2003A
Gnd
C7
L1
R6
Vsns1
R7
R6
Fb1
R7
C8
L2
R8
Vsns2
R9
R8
Fb2
R9
Vout1
C9
Vout2
C10
Vo2 Vo2
Ratiometric Powerup Ratiometric Powerdown
Vo1 Vo1
Vo2 Vo2
Simultaneous Powerup Simultaneous Powerdown
Fig. 1: Power Up /Down Sequencing
ORDERING INFORMATION
PKG PACKAGE
DESIG DESCRIPTION
M IR3623MPbF
M IR3623MTRPbF
PIN
COUNT
32
32
PARTS
PER TUBE
73
--------
PARTS
PER REEL
-------
6000
T&R
ORIANTAION
Fig A
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Pin#
Pin Name
1 PGood1
2 PGood2
3 Track2
4 VSEN2
5 OVP-Output
6 Fb2
7 Comp2
8 SS2/SD2/Mode
9 OCSet2
10 Ph_En2
11 PWM2
12 Vcc
13 Vout3
14 PWM1
15 Ph_En1
16 OCSet1
17 SS1/SD1
IR3623MPbF
Description
Power Good pin out put for channel 1, open collector. This pin
needs to be externally pulled high
Power Good pin out put for channel 2, open collector. This pin
needs to be externally pulled high
Sets the type of power up / down sequencing (ratiometric or
simultaneously). If it is not used connect this pin to Vout3.
Sense pin for OVP2 and Power Good 2, Channel 2
OVP output, goes high when OVP condition occurs
Inverting inputs to the error amplifier2
Compensation pin for the error amplifier2
Soft start for channel 2, can be used as SD pin. Float this pin for
current share single output application
Current limit set point for channel2
Phase Enable pin for channel2
PWM output for channel2
Supply Voltage for the internal blocks of the IC
Output of the internal regulator
PWM output for channel1
Phase Enable pin for channel1
Current limit set point for Channel 1
Soft start for channel 1, can be used as SD pin
18 Comp1
19 Fb1
20 OCGnd
21 VSEN1
22 Track1
23 Sync
24 Seq
25 VP1
26 VP2
27 VREF
28 SGnd
29 Gnd
30 Rt
31 Enable
32 5V_sns
Compensation pin for the error amplifier1
Inverting input to the error amplifier1
Ground connection for OCset circuit
Sense pin for OVP1 and Power Good, Channel 1
Sets the type of power up / down sequencing (ratiometric or
simultaneously). If it is not used connect this pin to Vout3.
External synchronization pin
Enable pin for tracking and sequencing
Non inverting input of error amplifier1
Non inverting input of error amplifier2
Reference Voltage
Signal Ground
IC’s Ground
Connecting a resistor from this pin to ground sets the Switching
frequency
Enable pin, recycling this pin will rest OV, SS and Prebias latch
Sensing either external 5V or the Vout3
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Current Share Mode
This feature allows to connect both outputs
together to increase current handling capability of
the converter to support a common load. In
current sharing mode, error amplifier 1 becomes
the master which regulates the common output
voltage and the error amplifier 2 performs the
current sharing function, figure 6 shows the
configuration of error amplifiers.
In this mode IR3623 make sure the master
channel starts first followed by slave channel to
prevent any glitch during start up. This is done by
clamping the output of slave’s error amplifier until
the master channel generates the first PWM
signal.
At no load condition the slave channel may be
kept off depends on the offset of error amplifier.
Lossless Inductor Current Sensing
The IR3623 uses a lossless current sensing for
current share purposes. The inductor current is
sensed by connecting a series resistor and a
capacitor network in parallel with inductor and
measuring the voltage across the capacitor, this
voltage is proportional to the inductor current. As
shown in figure 6 the voltage across the
inductor’s DCR can be expressed by:
VRL 1 (s )
=
(V in
− Vout
)*
R L1
R L1 * sL1
- - - -(1 )
VRL 1 (s ) = IL1 * R L1
- - - -( 2 )
The voltage across the C1 can expressed by:
1
VC1 (s )
=
(V in
− Vout
)*
R1
sC 1
*
1
sC 1
- - - -( 3 )
Combining equations (1),(2) and (3) result to the
following expression for VC1:
VC1 (s )
=
IL1
*
R L1 + sL1
1 + sR 1 * C1
- - - -( 4 )
Usually the resistor R1 and C1 are chosen so that
the time constant of R1 and C1 equals the time
constant of the inductor which is the inductance
L1 over the inductor’s DCR (RL1). If the two time
constants match, the voltage across C1 is
proportional to the current through L1, and
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IR3623MPbF
Vin Master Phase
IL1
L1 RL1
+ VL1 (s) -
Q2 R1
C1
+ VC1(s) -
VP2 VOUT
FB2
Vin
Q3
R2
C2
L2
Q4
RL2
Slave Phase
Fig. 6: Loss Less inductor current sensing
and current sharing
the sense circuit can be treated as if only a
sense resistor with the value RL1 was used.
If
: R1
* C1
=
L1
R L1
VC (s ) ≈ IL1 * RL1
The mismatch of the time constant does not
affect the measurements of inductor DC current,
but affects the AC component of the inductor
current.
Soft-Start
The IR3623 has programmable soft-start to
control the output voltage rise and limit the inrush
current during start-up. It provides a separate
Soft-start function for each outputs. This will
enable to sequence the outputs by controlling the
rise time of each outputs through selection of
different value soft-start capacitors.
To ensure correct start-up, the soft-start
sequence initiates when the Vcc, Enable and
5V_sns rise above their threshold and generate
the Power On Reset (POR) signal. Soft-start
function operates by sourcing an internal current
to charge an external capacitor to about 3V.
Initially, the soft-start function clamps the error
amplifier’s output of the PWM converter.
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| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet IR3623MPBF.PDF ] | |
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