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PDF PCA9674 Data sheet ( Hoja de datos )

Número de pieza PCA9674
Descripción Remote 8-bit I/O expander
Fabricantes NXP Semiconductors 
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PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
Rev. 02 — 12 October 2006
Product data sheet
1. General description
The PCA9674/74A provide general purpose remote I/O expansion for most
microcontroller families via the two-line bidirectional bus (I2C-bus) and is a part of the
Fast-mode Plus (Fm+) family.
The PCA9674/74A is a drop-in upgrade for the PCF8574/74A providing higher Fast-mode
Plus I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM
dimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devices
can be on the bus without the need for bus buffers, higher total package sink capacity
(200 mA versus 100 mA) that supports having all LEDs on at the same time and more
device addresses (64 versus 8) are available to allow many more devices on the bus
without address conflicts.
The devices consist of an 8-bit quasi-bidirectional port and an I2C-bus interface. The
PCA9674/74A have low current consumption and include latched outputs with 25 mA high
current drive capability for directly driving LEDs.
They also possess an interrupt line (INT) that can be connected to the interrupt logic of
the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform
the microcontroller if there is incoming data on its ports without having to communicate via
the I2C-bus.
The internal Power-On Reset (POR) or Software Reset sequence initializes the I/Os as
inputs.
2. Features
I 1 MHz I2C-bus interface
I Compliant with the I2C-bus Fast and Standard modes
I SDA with 30 mA sink capability for 4000 pF buses
I 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
I 8-bit remote I/O pins that default to inputs at power-up
I Latched outputs with 25 mA sink capability for directly driving LEDs
I Total package sink capability of 200 mA
I Active LOW open-drain interrupt output
I 64 programmable slave addresses using 3 address pins
I Readable device ID (manufacturer, device type, and revision)
I Low standby current
I 40 °C to +85 °C operation
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101

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PCA9674 pdf
www.DNatXaSPheSete4Um.coicmonductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
6.2 Pin description
Table 2.
Symbol
AD0
AD1
AD2
P0
P1
P2
P3
VSS
P4
P5
P6
P7
INT
SCL
SDA
VDD
Pin description for DIP16, SO16, TSSOP16
Pin Description
1 address input 0
2 address input 1
3 address input 2
4 quasi-bidirectional I/O 0
5 quasi-bidirectional I/O 1
6 quasi-bidirectional I/O 2
7 quasi-bidirectional I/O 3
8 supply ground
9 quasi-bidirectional I/O 4
10 quasi-bidirectional I/O 5
11 quasi-bidirectional I/O 6
12 quasi-bidirectional I/O 7
13 interrupt output (active LOW)
14 serial clock line
15 serial data line
16 supply voltage
Table 3.
Symbol
INT
SCL
n.c.
SDA
VDD
AD0
AD1
n.c.
AD2
P0
P1
P2
n.c.
P3
VSS
P4
P5
n.c.
P6
P7
Pin description for SSOP20
Pin Description
1 interrupt output (active LOW)
2 serial clock line
3 not connected
4 serial data line
5 supply voltage
6 address input 0
7 address input 1
8 not connected
9 address input 2
10 quasi-bidirectional I/O 0
11 quasi-bidirectional I/O 1
12 quasi-bidirectional I/O 2
13 not connected
14 quasi-bidirectional I/O 3
15 supply ground
16 quasi-bidirectional I/O 4
17 quasi-bidirectional I/O 5
18 not connected
19 quasi-bidirectional I/O 6
20 quasi-bidirectional I/O 7
PCA9674_PCA9674A_2
Product data sheet
Rev. 02 — 12 October 2006
© NXP B.V. 2006. All rights reserved.
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PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
Fig 10. Device ID address
1 1 1 1 1 0 0 R/W
002aac116
7.2.1 Software Reset
The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up
state value through a specific formatted I2C-bus command. To be performed correctly, it
implies that the I2C-bus is functional and that there is no device hanging the bus.
The Software Reset sequence is defined as following:
1. A START command is sent by the I2C-bus master.
2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (write)
is sent by the I2C-bus master.
3. The PCA9674/74A device(s) acknowledge(s) after seeing the General Call address
‘0000 0000’ (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to
the I2C-bus master.
4. Once the General Call address has been sent and acknowledged, the master sends
1 byte. The value of the byte must be equal to 06h.
a. The PCA9674/74A acknowledges this value only. If the byte is not equal to 06h, the
PCA9674/74A does not acknowledge it.
If more than 1 byte of data is sent, the PCA9674/74A does not acknowledge any
more.
5. Once the right byte has been sent and correctly acknowledged, the master sends a
STOP command to end the Software Reset sequence: the PCA9674/74A then resets
to the default value (power-up value) and is ready to be addressed again within the
specified bus free time. If the master sends a Repeated START instead, no reset is
performed.
The I2C-bus master must interpret a non-acknowledge from the PCA9674/74A (at any
time) as a ‘Software Reset Abort’. The PCA9674/74A does not initiate a reset of its
registers.
The unique sequence that initiates a Software Reset is described in Figure 11.
SWRST Call I2C-bus address
SWRST data = 06h
S0 0 0 0 0 0 0 0A0 0 0 0 0 1 1 0AP
START condition
R/W
acknowledge
acknowledge
from slave(s)
from slave(s)
PCA9674/74A is(are) reset.
Registers are set to default power-up values.
002aac262
Fig 11. Software Reset sequence
PCA9674_PCA9674A_2
Product data sheet
Rev. 02 — 12 October 2006
© NXP B.V. 2006. All rights reserved.
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