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PDF PCA9673 Data sheet ( Hoja de datos )

Número de pieza PCA9673
Descripción Remote 16-bit I/O expander
Fabricantes NXP Semiconductors 
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PCA9673
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and
reset
Rev. 01 — 1 February 2007
Product data sheet
1. General description
The PCA9673 provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional bus (I2C-bus) and is a part of the Fast-mode Plus
family.
The PCA9673 is a drop in upgrade for the PCF8575 providing higher Fast-mode Plus
(Fm+) I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM
dimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devices
can be on the bus without the need for bus buffers, higher total package sink capacity
(400 mA versus 100 mA) that supports having all 25 mA LEDs on at the same time and
more device addresses (16 versus 8) are available to allow many more devices on the bus
without address conflicts.
The difference between the PCA9673 and the PCF8575 is that the A2 address pin is
replaced by a RESET input on the PCA9673.
The device consists of a 16-bit quasi-bidirectional port and an I2C-bus interface. The
PCA9673 has a low current consumption and includes latched outputs with 25 mA high
current drive capability for directly driving LEDs.
It also possesses an interrupt line (INT) which can be connected to the interrupt logic of
the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform
the microcontroller if there is incoming data on its ports without having to communicate via
the I2C-bus.
The internal Power-On Reset (POR), hardware reset pin (RESET) or software reset
sequence initializes the I/Os as inputs.
2. Features
I 1 MHz I2C-bus interface
I Compliant with the I2C-bus Fast and Standard modes
I SDA with 30 mA sink capability for 4000 pF buses
I 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
I 16-bit remote I/O pins that default to inputs at power-up
I Latched outputs with 25 mA sink capability for directly driving LEDs
I Total package sink capability of 400 mA
I Active LOW open-drain interrupt output
I 16 programmable slave addresses using 2 address pins
I Readable device ID (manufacturer, device type, and revision)

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PCA9673 pdf
www.DNatXaSPheSete4Um.coicmonductors
PCA9673
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and reset
terminal 1
index area
P00 1
P01 2
P02 3
P03 4
P04 5
P05 6
PCA9673BS
18 AD0
17 P17
16 P16
15 P15
14 P14
13 P13
terminal 1
index area
AD1 2
RESET 3
P00 4
P01 5
P02 6
P03 7
P04 8
P05 9
P06 10
P07 11
PCA9673BQ
23 SDA
22 SCL
21 AD0
20 P17
19 P16
18 P15
17 P14
16 P13
15 P12
14 P11
Transparent top view
002aac305
Fig 7. Pin configuration for HVQFN24
Transparent top view
002aac306
Fig 8. Pin configuration for DHVQFN24
6.2 Pin description
Table 2.
Symbol
INT
AD1
RESET
P00
P01
P02
P03
P04
P05
P06
P07
VSS
P10
P11
P12
P13
P14
P15
P16
P17
AD0
Pin description
Pin
SO24, SSOP24,
TSSOP24, DHVQFN24
1
2
3
4
5
6
7
8
9
10
11
12[1]
13
14
15
16
17
18
19
20
21
Description
HVQFN24
22 interrupt output (active LOW)
23 address input 1
24 reset input (active LOW)
1 quasi-bidirectional I/O 00
2 quasi-bidirectional I/O 01
3 quasi-bidirectional I/O 02
4 quasi-bidirectional I/O 03
5 quasi-bidirectional I/O 04
6 quasi-bidirectional I/O 05
7 quasi-bidirectional I/O 06
8 quasi-bidirectional I/O 07
9[1] supply ground
10 quasi-bidirectional I/O 10
11 quasi-bidirectional I/O 11
12 quasi-bidirectional I/O 12
13 quasi-bidirectional I/O 13
14 quasi-bidirectional I/O 14
15 quasi-bidirectional I/O 15
16 quasi-bidirectional I/O 16
17 quasi-bidirectional I/O 17
18 address input 0
PCA9673_1
Product data sheet
Rev. 01 — 1 February 2007
© NXP B.V. 2007. All rights reserved.
5 of 33

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PCA9673 arduino
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PCA9673
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and reset
first data byte is acknowledged by the PCA9673, the second data byte P17 to P10 is sent
by the master. Once again, the PCA9673 acknowledges the receipt of the data. Each 8-bit
data is presented on the port lines after it has been acknowledged by the PCA9673.
The number of data bytes that can be sent successively is not limited. After every two
bytes, the previous data is overwritten.
The first data byte in every pair refers to Port 0 (P07 to P00), whereas the second data
byte in every pair refers to Port 1 (P17 to P10). See Figure 15.
first byte
second byte
07 06 05 04 03 02 01 00 A 17 16 15 14 13 12 11 10 A
P07 P06 P05 P04 P03 P02 P01 P00
P17 P16 P15 P14 P13 P12 P11 P10
002aab634
Fig 15. Correlation between bits and ports
SCL 1 2 3 4 5 6 7 8 9
slave address
data to port 0
data to port 1
SDA S A6 A5 A4 A3 A2 A1 A0 0
A
PP
07 06
1
PPPPP
04 03 02 01 00
A
P
17
1
PPPPPP
15 14 13 12 11 10
A
START condition
write to port
data output from port
R/W
P05
acknowledge
from slave
P16
acknowledge
from slave
acknowledge
from slave
tv(Q)
data A0 and B0 valid
tv(Q)
data A0 and B0 valid
P05 output voltage
P05 pull-up output current
P16 output voltage
Itrt(pu)
IOH
P16 pull-up output current
INT
td(rst)
Itrt(pu)
IOH
002aab632
Fig 16. Write mode (output)
8.3 Reading from a port (Input mode)
All ports programmed as input should be set to logic 1. To read, the master
(microcontroller) first addresses the slave device after it receives the interrupt. By setting
the last bit of the byte containing the slave address to logic 1 the Read mode is entered.
The data bytes that follow on the SDA are the values on the ports. If the data on the input
port changes faster than the master can read, this data may be lost.
PCA9673_1
Product data sheet
Rev. 01 — 1 February 2007
© NXP B.V. 2007. All rights reserved.
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