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PDF FS6051 Data sheet ( Hoja de datos )

Número de pieza FS6051
Descripción (FS6050 - FS6054) LOW-SKEW CLOCK FANOUT BUFFER ICs
Fabricantes AMI 
Logotipo AMI Logotipo



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No Preview Available ! FS6051 Hoja de datos, Descripción, Manual

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April 1999
1.0 Features
Generates up to eighteen low-skew, non-inverting
clocks from one clock input
Supports up to four SDRAM DIMMs
Uses either I2C-bus or SMBus serial interface with
Read and Write capability for individual clock output
control
Output enable pin tristates all clock outputs to facili-
tate board testing
Clock outputs skew-matched to less than 250ps
Less than 5ns propagation delay
Output impedance: 17at 0.5VDD
Serial interface I/O meet I2C specifications; all other
I/O are LVTTL/LVCMOS-compatible
Five differerent pin configurations available:
FS6050: 18 clock outputs in a 48-pin SSOP
FS6051: 10 clock outputs in a 28-pin SOIC, SSOP
FS6053: 13 clock outputs in a 28-pin SOIC
FS6054: 14 clock outputs in a 28-pin SOIC
2.0 Description
The FS6050 family of CMOS clock fanout buffer ICs are
designed for high-speed motherboard applications, such
as Intel Pentium® II PC100-based systems with 100MHz
SDRAM.
Up to eighteen buffered, non-inverting clock outputs are
fanned-out from one clock input. Individual clocks are
skew matched to less than 250ps at 100MHz. Multiple
power and ground supplies reduce the effects of supply
noise on device performance.
Under I2C-bus control, individual clock outputs may be
turned on or off. An active-low output enable is available
to force all the clock outputs to a tristate level for system
testing.
Figure 2: Pin Configuration (FS6050)
Figure 1: Block Diagram (FS6050)
VDD_I2C
SDA
SCL
VSS_I2C
CLK_IN
Serial
Interface
18
OE
FS6050
VDD
SDRAM_(0:1)
VSS
VDD
SDRAM_(2:3)
VSS
VDD
SDRAM_(4:5)
VSS
VDD
SDRAM_(6:7)
VSS
VDD
SDRAM_(8:9)
VSS
VDD
SDRAM_(10:11)
VSS
VDD
SDRAM_(12:13)
VSS
VDD
SDRAM_(14:15)
VSS
VDD
SDRAM_16
VSS
VDD
SDRAM_17
VSS
FS6050
48-pin SSOP
Figure 3: Pin Configuration (FS6051)
FS6051
28-pin SOIC, SSOP
Additional pin configurations are noted on Page 2.
Intel and Pentium are registered trademarks of Intel Corporation. I2C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc. reserves the right to change the detail specifica-
tions as may be required to permit improvements in the design of its products.
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FS6051 pdf
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April 1999
4.0 Dual Serial Interface Control
This integrated circuit is a read/write slave device that
supports both the Inter IC Bus (I2C-bus) and the System
Management Bus (SMBus) two-wire serial interface pro-
tocols. The unique device address that is written to the
device determines whether the part expects to receive
SMBus commands or I2C commands. Since SMBus is
derived from the I2C-bus, the protocol for both bus types
is very similar.
In general, the bus has to be controlled by a master de-
vice that generates the serial clock SCL, controls bus
access, and generates the START and STOP conditions
while the device works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated. A device that
sends data onto the bus is defined as the transmitter, and
a device receiving data as the receiver.
Bus logic levels and timing parameters noted herein fol-
low I2C-bus convention. Logic levels are based on a per-
centage of VDD. A logic-one corresponds to a nominal
voltage of VDD, while a logic-zero corresponds to ground
(VSS).
4.1 Bus Conditions
Data transfer on the bus can only be initiated when the
bus is not busy. During the data transfer, the data line
(SDA) must remain stable whenever the clock line (SCL)
is high. Changes in the data line when the clock line is
high is interpreted by the device as a START or STOP
condition. Both I2C-bus and SMBus protocols define the
following conditions on the bus. Refer to Figure 12: Bus
Timing Data for more information.
4.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
4.1.2 START Data Transfer
A high to low transition of the SDA line while the SCL in-
put is high indicates a START condition. All commands to
the device must be preceded by a START condition.
4.1.3 STOP Data Transfer
A low to high transition of the SDA line while SCL is held
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.
4.1.4 Data Valid
The state of the SDA line represents valid data if the SDA
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the
SDA line must be changed only during the low period of
the SCL signal. There is one clock pulse per data bit.
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions
is determined by the master device, and can continue
indefinitely. However, data that is overwritten to the de-
vice after the data registers are filled will overflow from
the last register into the first register, then the second,
and so on, in a first-in, first-overwritten fashion.
4.1.5 Acknowledge
When addressed, the receiving device is required to gen-
erate an Acknowledge after each byte is received. The
master device must generate an extra clock pulse to co-
incide with the Acknowledge bit. The acknowledging de-
vice must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
The master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been read (clocked) out of the slave. In this case, the
slave must leave the SDA line high to allow the master to
generate a STOP condition.
4.2 Bus Operation and Commands
All programmable registers can be accessed via the bi-
directional two wire digital interface. The device accepts
the Random Register Read/Write and the Sequential
Register Read/Write I2C commands. The device also
supports the Block Read/Write SMBus commands.
4.2.1 I2C-bus and SMBus Device Addressing
After generating a START condition, the bus master
broadcasts a seven-bit device address followed by a R/W
bit. Note that every device on an I2C-bus or SMBus must
have a unique address to avoid bus conflicts.
For an SMBus interface, the address of the device is:
A6 A5 A4 A3 A2 A1 A0
1101001
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April 1999
Table 10: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP. MAX. UNITS
Overall
Clock Skew, Maximum;
SDRAM_0 to any SDRAM pin *
tskw
Measured on the rising edge at 1.5V;
CL = 20pF
66.67
100
tPLH(min)
Measured on the rising edge at 1.5V;
CL = 20pF
66.67
100
Propagation Delay, Average;
CLK_IN to any SDRAM pin *
tPLH(max)
tPHL(min)
Measured on the rising edge at 1.5V;
CL = 30pF
Measured on the rising edge at 1.5V;
CL = 20pF
66.67
100
66.67
100
tPHL(max)
Measured on the rising edge at 1.5V;
CL = 30pF
66.67
100
Clock Outputs (SDRAM_0:17 3.3V Type 4 Clock Buffer)
Rise Time *
tr(min)
tr(max)
VO = 0.4V to 2.4V; CL = 20pF
VO = 0.4V to 2.4V; CL = 30pF
66.67
100
66.67
100
Fall Time *
tf(min)
tf(max)
VO = 2.4V to 0.4V; CL = 20pF
VO = 2.4V to 0.4V; CL = 30pF
66.67
100
66.67
100
Clock High Time *
tKH(min)
VO = 2.4V; CL = 20pF
tKH(max)
VO = 2.4V; CL = 30pF
66.67
100
66.67
100
Clock Low Time *
tKL(min)
VO = 0.4V; CL = 20pF
tKL(max)
VO = 0.4V; CL = 30pF
66.67
100
66.67
100
Duty Cycle *
From rising edge to rising edge at
1.5V; CL = 20pF
From rising edge to rising edge at
1.5V; CL = 30pF
66.67
100
66.67
100
Tristate Enable Delay *
Tristate Disable Delay *
tPZL
Output tristated to output active; CL = 20pF
tPZH
tPLZ
Output active to output tristated; CL = 20pF
tPHZ
182
228
3.7
3.8
3.7
4.0
3.9
3.8
4.2
4.0
1.0
0.9
1.2
1.0
1.0
0.7
1.1
0.8
6.5
3.8
6.5
3.8
6.5
4.6
6.3
4.5
49
45
50
46
4.7
4.6
6.3
7.9
ps
ns
ns
ns
ns
ns
%
ns
ns
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