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PDF FS6011-02 Data sheet ( Hoja de datos )
| Número de pieza | FS6011-02 | |
| Descripción | DIGITAL AUDIO/VIDEO CLOCK GENERATOR IC | |
| Fabricantes | AMI | |
| Logotipo |  |
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1.0 Features
• Triple phase-locked loop (PLL) device provides exact
ratiometric derivation of Audio, Processor, and Utility
Clocks
• On-chip tunable voltage-controlled crystal oscillator
(VCXO) allows precise system frequency tuning
• Serial interface for Audio and Utility Clock frequency
selection
• Board-programmable Processor Clock frequency
selection
• Supports 32, 44.1, and 48kHz 256x oversampled
DACs as well as 384x at 44.1kHz and 512x at 48kHz
• Tunable Audio Clock frequencies for undetectable
resynchronization of audio and video streams
• Small circuit board footprint (16-pin 0.150″ SOIC)
• Custom frequency selections available - contact your
local AMI Sales Representative for more information
2.0 Description
The FS6011-02 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
At the core of the FS6011-02 is circuitry that implements
a voltage-controlled crystal oscillator when an external
resonator (nominally 27MHz) is attached. The VCXO al-
lows device frequencies to be precisely adjusted for use
in systems that have frequency matching requirements,
such as digital satellite receivers.
Three high-resolution phase-locked loops independently
generate three other selectable frequencies derived from
the VCXO frequency. These clock frequencies are re-
lated to the VCXO frequency and to each other by exact
ratios. The locking of all the output frequencies together
can eliminate unpredictable artifacts in video systems
and unpredictable electromagnetic interference (EMI)
performance due to frequency harmonic stacking.
Figure 1: Block Diagram
PSEL0
PSEL1
Processor
Clock PLL
XTUNE
XIN
XOUT
VCXO
Audio
Clock PLL
Utility
Clock PLL
SLOAD
SCLK
SDATA
Serial
Interface
FS6011
PCLK
ACLK
UCLK
CLK_27
Figure 2: Pin Configuration
SCLK 1
SDATA 2
SLOAD 3
VSS 4
XIN 5
XOUT 6
XTUNE 7
VDD 8
16 CLK27
15 ACLK
14 VDD
13 UCLK
12 PCLK
11 VSS
10 PSEL0
9 PSEL1
16-pin (0.150″) SOIC
American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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4.5 Reference Frequencies (CLK27)
The CLK27 output frequency is controlled by register bit
D[8] that selects either the VCXO reference frequency or
the UCLK frequency.
Table 7: CLK27 Frequency Select
D[8]
CLK27 Output
0 VCXO Frequency
1 UCLK Frequency
4.6 VCXO Coarse Tuning and Enable
The VCXO may be coarse tuned by a programmable ad-
justment of the crystal load capacitance via D[12:9]. The
actual amount of frequency warping caused by the tuning
capacitance will depend on the crystal used. The VCXO
tuning capacitance includes an external 6pF load ca-
pacitance (12pF from the XIN pin to ground and 12pF
from the XOUT pin to ground).
The fine tuning capability of the VCXO can be enabled by
setting D[13] to a logic-one or disabled by clearing the bit
to a logic-zero.
Table 8: VCXO Tuning Capacitance
D[12]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D[11]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D[10]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D[9]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VCXO TUNING
CAPACITANCE (pF)
10.00
10.84
11.69
12.53
13.38
14.22
15.06
15.91
16.75
17.59
18.43
19.28
20.13
20.97
21.81
22.66
Figure 4 shows the typical effect of the coarse and fine
tuning mechanisms. The difference in VCXO frequency in
parts-per-million (ppm) is shown as the fine tuning volt-
age on the XTUNE pin varies from 0V to 5V. The coarse
tune range as shown is about 350ppm. As the crystal
load capacitance is increased (with increasing Coarse
Tune setting) the frequency is pulled somewhat less with
each coarse step and the fine tuning range decreases.
The fine tuning range always overlaps a few coarse tun-
ing ranges, eliminating the possibility of holes in the
VCXO response. Note that different crystal warping char-
acteristics will change the scaling on the Y-axis, but not
the overall characteristic of the curves.
Figure 4: VCXO Coarse and Fine Tuning
VCXO Range (ppm) vs. XTUNE Voltage (V)
200
150
100
50
0
-50
XTUNE Voltage = 0.0V
XTUNE Voltage = 5.0V
-100
-150
-200
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Coarse Tune Setting D[11:14]
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6.0 Package Information
Table 16: 16-pin SOIC (0.150") Package Dimensions
DIMENSIONS
INCHES
MILLIMETERS
MIN. MAX. MIN. MAX.
A 0.061 0.068 1.55 1.73
A1 0.004 0.0098 0.102 0.249
A2 0.055 0.061 1.40 1.55
B 0.013 0.019 0.33 0.49
C 0.0075 0.0098 0.191 0.249
D 0.386 0.393 9.80 9.98
E 0.150 0.157 3.81 3.99
e 0.050 BSC
1.27 BSC
H 0.230 0.244 5.84 6.20
h 0.010 0.016 0.25 0.41
L 0.016 0.035 0.41 0.89
Θ 0° 8° 0° 8°
16
R
ÅÉ"ÇÅÃÇ"#)#$É#ÃÇ
EH
1
B
BASE PLANE
e
D
ALL RADII:
0.005" TO 0.01"
A2 A
A1
SEATING PLANE
C
h x 45°
L
7° typ.
θ
Table 17: 16-pin SOIC (0.150") Package Characteristics
PARAMETER
Thermal Impedance, Junction to Free-Air
Lead Inductance, Self
Lead Inductance, Mutual
Lead Capacitance, Bulk
SYMBOL
ΘjA
L11
L12
C11
CONDITIONS/DESCRIPTION
Air flow = 0 m/s
Corner lead
Center lead
Any lead to any adjacent lead
Any lead to VSS
TYP.
108
4.0
3.0
0.4
0.5
UNITS
°C/W
nH
nH
pF
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