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PDF M34552 Data sheet ( Hoja de datos )

Número de pieza M34552
Descripción SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Fabricantes Renesas Technology 
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No Preview Available ! M34552 Hoja de datos, Descripción, Manual

4552 Groupwww.DataSheet4U.com
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
REJ03B0023-0302
Rev.3.02
2006.12.22
DESCRIPTION
The 4552 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a
simple, high-speed instruction set. The computer is equipped with
two 8-bit timers (each timer has one or two reload registers), a 16-
bit timer for clock count, interrupts, and oscillation circuit switch
function.
The various microcomputers in the 4552 Group include variations
of the built-in memory size as shown in the table below.
FEATURES
qMinimum instruction execution time
Mask ROM version .............................................................. 0.5 µs
(at 6 MHz oscillation frequency, in high-speed through-mode)
One Time PROM version ................................................... 0.68 µs
(at 4.4 MHz oscillation frequency, in high-speed through-mode)
qSupply voltage
Mask ROM version ...................................................... 1.8 to 5.5 V
One Time PROM version ............................................. 1.8 to 3.6 V
(It depends on operation source clock, oscillation frequency and op-
eration mode)
q Timers
Timer 1 ...................................... 8-bit timer with a reload register
Timer 2 ................................. 8-bit timer with two reload registers
Timer 3 .............................. 16-bit timer (fixed dividing frequency)
qInterrupt ........................................................................ 4 sources
qKey-on wakeup function pins ..................................................... 9
q LCD control circuit
Segment output ........................................................................ 28
Common output .......................................................................... 4
qVoltage drop detection circuit (only H version)
Reset occurrence .................................... Typ. 1.8 V (Ta = 25 °C)
Reset release .......................................... Typ. 1.9 V (Ta = 25 °C)
qWatchdog timer
qClock generating circuit
Built-in clock
(on-chip oscillator)
Main clock
(ceramic resonator/RC oscillation)
Sub-clock
(quartz-crystal oscillation)
qLED drive directly enabled (port D)
APPLICATION
Remote control transmitter
Part number
M34552M4-XXXFP
M34552M8-XXXFP
M34552G8FP (Note)
M34552M4H-XXXFP
M34552M8H-XXXFP
M34552G8HFP (Note)
Note: Shipped in blank.
ROM (PROM) size
(10 bits)
4096 words
8192 words
8192 words
4096 words
8192 words
8192 words
RAM size
(4 bits)
288 words
288 words
288 words
288 words
288 words
288 words
Package
48P6S-A
48P6S-A
48P6S-A
48P6S-A
48P6S-A
48P6S-A
ROM type
Mask ROM
Mask ROM
One Time PROM
Mask ROM
Mask ROM
One Time PROM
Rev.3.02 Dec 22, 2006 page 1 of 142
REJ03B0023-0302

1 page




M34552 pdf
4552 Group
www.DataSheet4U.com
PIN DESCRIPTION
Pin Name
VDD Power supply
VSS Ground
CNVSS
CNVSS
RESET
Reset input/output
XIN
XOUT
XCIN
XCOUT
D0D5
D6, D7
Main clock input
Main clock output
Sub-clock input
Sub-clock output
I/O port D
Input is examined by
skip decision.
Output port D
P00P03 I/O port P0
P10P13 I/O port P1
P20P23 I/O port P2
Port C
Output port C
COM0
COM3
Common output
SEG0SEG28 Segment output
(Note)
CNTR
Timer input/output
INT Interrupt input
Input/Output
Function
Connected to a plus power supply.
Connected to a 0 V power supply.
Connect CNVSS to VSS and apply L(0V) to CNVSS certainly.
I/O An N-channel open-drain I/O pin for a system reset. When the SRST instruction,
watchdog timer, the built-in power-on reset or the voltage drop detection circuit
causes the system to be reset, the RESET pin outputs Llevel.
Input
Output
I/O pins of the main clock generating circuit. When using a ceramic resonator, con-
nect it between pins XIN and XOUT. A feedback resistor is built-in between them.
When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave
XOUT pin open.
Input
Output
I/O pins of the sub-clock generating circuit. Connect a 32.768 kHz quartz-crystal oscilla-
tor between pins XCIN and XCOUT. A feedback resistor is built-in between them. XCIN and
XCOUT pins are also used as ports D6 and D7, respectively.
I/O Each pin of port D has an independent 1-bit wide I/O function. The output structure
can be switched to N-channel open-drain or CMOS by software. For input use, set
the latch of the specified bit to 1and select the N-channel open-drain. Port D5 is
also used as INT pin.
Output
Each pin of port D has an independent 1-bit wide output function. The output struc-
ture is N-channel open-drain. Ports D6 and D7 are also used as XCIN pin and XCOUT
pin, respectively.
I/O Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
1and select the N-channel open-drain. Port P0 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software. Ports P00P03 are
also used as SEG21SEG24, respectively.
I/O Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
1and select the N-channel open-drain. Port P1 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software. Ports P10P13 are
also used as SEG25SEG28, respectively.
I/O Port P2 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
1and select the N-channel open-drain.
Ports P20P23 are also used as SEG17SEG20, respectively.
Output 1-bit output port. The output structure is CMOS. Port C is also used as CNTR pin.
Output LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0
COM2 are used at 1/3 duty and pins COM0COM3 are used at 1/4 duty.
Output
LCD segment output pins. SEG0SEG2 pins are used as VLC3VLC1 pins, respec-
tively. SEG17SEG28 pins are used as Ports P20P23, Ports P00P03 and Ports
P10P13, respectively.
I/O CNTR pin has the function to input the clock for the timer 1 event counter and to out-
put the PWM signal generated by timer 2.CNTR pin is also used as Port C.
Input
INT pin accepts external interrupts. They have the key-on wakeup function which can
be switched by software. INT pin is also used as Port D5.
Note: SEG13 pin is not existed in the 4552 Group.
MULTIFUNCTION
Pin Multifunction
Pin Multifunction
Pin Multifunction
Pin
XCIN
D6
D6 XCIN
P20 SEG17
SEG17
XCOUT
D7
D7 XCOUT
P21 SEG18
SEG18
P00 SEG21
SEG21 P00
P22 SEG19
SEG19
P01 SEG22
SEG22 P01
P23 SEG20
SEG20
P02 SEG23
SEG23 P02
D5 INT
INT
P03 SEG24
SEG24 P03
C CNTR
CNTR
P10 SEG25
SEG25 P10
SEG0
VLC3
VLC3
P11 SEG26
SEG26 P11
SEG1
VLC2
VLC2
P12 SEG27
SEG27 P12
SEG2
VLC1
VLC1
P13 SEG28
SEG28 P13
Notes 1: Pins except above have just single function.
2: The input/output of D5 can be used even when INT is selected.
The threshold value is different between port D5 and INT. Accordingly, be careful when the input of both is used.
3: The port C Houtput function can be used even when CNTR (output) is selected.
Multifunction
P20
P21
P22
P23
D5
C
SEG0
SEG1
SEG2
Rev.3.02 Dec 22, 2006 page 5 of 142
REJ03B0023-0302

5 Page





M34552 arduino
4552 Group
www.DataSheet4U.com
LCD power supply
LCD control
signal
key-on
wakeup
input
K11 Edge detection
0 circuit
1 Level detection
circuit
K10
0
1
K02
IAP1
Register A instruction
C2j
Aj
FR02
LCD power
supply
Aj
OP1A instruction
D
TQ
C2j
01
(Note 1)
P10/SEG25, P11/SEG26
(Note 1)
Pull-up transistor
PU1j
LCD power supply
LCD control
signal
key-on
wakeup
input
K13 Edge detection
0 circuit
Level detection
1
circuit
K12
0
1
K03
IAP1
Register A instruction
C2k
Ak
FR03
LCD power
supply
Ak
OP1A instruction
D
TQ
C2k
01
(Note 1)
P12/SEG27, P13/SEG28
(Note 1)
Pull-up transistor
PU1k
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: j represents bits 0 and 1.
4: k represents bits 2 and 3.
Port block diagram (4)
Rev.3.02 Dec 22, 2006 page 11 of 142
REJ03B0023-0302

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