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PDF M65881AFP Data sheet ( Hoja de datos )

Número de pieza M65881AFP
Descripción Digital Amplifier Processor
Fabricantes Renesas Technology 
Logotipo Renesas Technology Logotipo



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M65881AFPwww.DataSheet4U.com
Digital Amplifier Processor of S-Master* Technology
REJ03F0004-0100Z
Rev.1.00
2003.05.08
DESCRIPTION
The M65881AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal
to high precise switching-pulse digital output without analog processing.
The M65881AFP has built-in 24bit sampling rate converter and digital-gain-controller.
The M65881AFP enables to realize high precise ( X`tal oscillation accuracy.) full digital amplifier systems combining with power
driver IC.
FEATURES
•Built-in 24bit Sampling Rate Converter.
Input Signal Sampling Rate from 32KHz to 192KHz (24bit Maximum).
4 kinds of Digital Input Format.
•Built-in L/R Independent Digital Gain Control.
•Built-in Soft Mute Function with Exponential Approximate-Curve.
•Correspondence to Output for Headphone.
MAIN SPECIFICATION
•Master Clock
Primary Clock: 256Fsi/512Fsi Secondary Clock: 1024Fso/512Fso
•Input Signal Format:
MSB First Right Justified(16/20/24bit),MSB First Left Justified(24bit)
LSB First Right Justified(24bit),I2S(24bit)
•Input Signal Sampling Rate from 32kHz to 192kHz.
•Gain Control Function:
+30dB~-dB (0.1dB Step until -96dB, -138dB Minimum)
•Third Order ∆Σ (16Fso:6bit/5bit,32Fso:5bit)
OUTLINE : 42P2R
0.8mm pitch 42pin SSOP
APPLICATION
DVD Receiver, AV Amplifier
RECOMMENDED OPERATING CONDITIONS
Logic Block:1.8V±10%,PWM Buffer Block :3.3V±10%
SYSTEM BLOCK DIAGRAM)
M65881AFP
CD
DVD Audio
etc.
LRCK
BCK
DATA
24bit
32kHz
to
192kHz
Sampling
Rate
Converter
Level
Control
+30dB
to
-
∆Σ PWM
256fsi/512fsi
Clock
MCU I/F
Clock
1024fso/512fso
* "S-Master" is the digital amplifier technology developed by Sony Corporation. "S-Master" is a trademark of Sony Corporation.
Rev.1.00 2003.05.08 page 1 of 23
Stream
Power
Driver
LC
Filter
Stream
Power
Driver
LC
Filter
Output
for Headphone

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M65881AFP pdf
M65881AFP
www.DataSheet4U.com
CHARACTERISTICS EVALUATION CIRCUIT
OUTL1 2
OUTL2 4
-
+
+
-
OUTR2 39
LRCK 16
BCK 17
DATA 18
OUTR1 41
M65881AFP
HPOUTL1 33
HPOUTL2 31
-
+
+
-
-
+
-
+
+
-
HPOUTR2 27
HPOUTR1 29
+
-
+
-
GND
+
-
GND
Power Supply
GND
Reference characteristic
Output for S/N 102dB(typ)
Power Stage THD+N 0.002%(typ)
Output for
S/N
100dB(typ)
Headphone THD+N 0.006%(typ)
Conditions
• Input :1kHz 0dB Full scale sine wave
• FS :Primary clock 44.1kHz, Secondary clock 48kHz
• PWM Output format 1 • AC dithering E • DC dithering : 0.1%
• Gain data setting : (Index) 10000b/ (Mantissa) 10000000b
• THD+N: Filter 20kHz LPF S/N: Filter 22kHz LPF + JIS-A
Rev.1.00 2003.05.08 page 5 of 23

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M65881AFP arduino
M65881AFP
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8. HPOUTL1, HPOUTL2, HPOUTR1, HPOUTR2
HPOUTL1, HPOUTL2, HPOUTR1 and HPOUTR2 are output pins for Headphone output.
PWM output modulated ∆Σ output data to pulse width.
The Phase of PWM Output for Power Stage and PWM Output for Headphone.
The output for Headphone is reverse phase as output for Power.
Moreover, it is possible to set L1 and R1 output same phase by serial control the system 1 mode,
bit24= "H"( PWMHP ).
In addition, NSPMUTE, PGMUTE and CHSEL are set in common PWM for Power
and PWM for Headphone, and as for CHRSEL flag is set as a function of only PWM for Power.
( Refer to previous page "Table of PWM control" for details ).
9. NSPMUTE
NSPMUTE pin sets to PWM Output to Duty 50% Mute.
L: PWM Output 50% Mute
H: Mute release
10. INIT
INIT is the pin for reset to all functions of M65881AFP.
"L" level: (1) Clear of data memory, (2) Initialization of a serial control setting
(3) PWM Output Duty 50% Mute
( " L" period needs more than 5msec.)
"H" level : Usual operation.
*The rise edge from "L" to "H": Re-synchronization are operated, which is same at serial control SYNC
function. (system2 mode bit6)
11. TEST1, TEST2
TEST1 and TEST2 pins are test input for factory shipping test of M65881AFP.
TEST1 and TEST2 pins must be tied to "L" level on usual operation.
12. Power supply and GND
Power supply and GND routes have a following 6 isolated lines.
(1) VddL, VssL,VddR, VssR, VssLR
VddL, VssL,VddR, VssR and VssLR pins are Power supply and GND for PWM Output buffer.
Lch and Rch have a independent power supply and GND. Power supply must be fixed at 3.3V.
(2) HPVddL, HPVssL, HPVddR, HPVssR
HPVddL, HPVssL, HPVddR and HPVssR pins are Power supply and GND of PWM Output
buffer for Headphone. Lch and Rch have a independent power supply and GND.
Power supply must be fixed at 3.3V.
(3) XVdd, XVss
XVdd and XVss are Power supply and GND for XfsoIN clock input block.
Power supply voltage must be fixed at 3.3V.
(4) XOVdd, XOVss
XOVdd and XOVss are Power supply and GND for XfsoOUT Clock Output.
Power supply voltage must be fixed at 3.3V
(5) DVdd, DVss
DVdd, DVss are Power supply and GND for internal digital block.
Power supply voltage must be fixed at 1.8V.
(6) BFVdd, BFVss
BFVdd and BFVss are Power and GND for input/output buffer (except for PWM block
and clock buffer). Power supply voltage must be fixed at 3.3V.
Rev.1.00 2003.05.08 page 11 of 23

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