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PDF CH5101A Data sheet ( Hoja de datos )
| Número de pieza | CH5101A | |
| Descripción | CMOS Monochrome Digital Video Camera | |
| Fabricantes | Chrontel | |
| Logotipo |  |
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CHRONTEL
CH5101A
CMOS Monochrome Digital Video Camera
Features
• 352 x 288 monochrome active pixel array, 1/3 inch lens
format ¥
• Programmable formats CIF 352x288, QCIF 176x144,
CCIR601 704x288
• Digital output CCIR601 4:2:2 (8-bit)
• Multidimensional automatic shutter control
• Below 1 LUX sensitivity
• Programmable I2C Serial bus control:
- Frame rate: 30fps-1fps in eight steps
- Gamma correction
- Shutterspeed
- Analog gain
- 16 backlight compensation zones
- Black clamp level
- Power down modes
• Stand-alone 25fps PAL and 30fps NTSC operation
with all automatic features
• Single crystal operation: Video timing on-chip
• Single 5V power supply
• Less than 0.5 watt power dissipation
¥ Patent number x,xxx,xxx patents pending
Description
The CH5101 is a single chip active pixel CMOS
monochrome video camera with digital video output in
several formats. Using sophisticated noise correction
circuitry to minimize fixed pattern noise and dark current
effects, the CH5101 provides a supurb quality picture in a
low cost device.
The CH5101 uses a proprietary autoshutter algorithm to
dynamically control the shutter time, analog gain, and
black clamp level, providing optimum picture and contrast
under all lighting conditions. The CH5101 also
incorporates extensive on-chip programmable digital
signal processing to maximize the usefulness of the device
in processor driven applications. This includes 16
programmable zones for backlight compensation,
allowing the user to adjust the image to their unique
lighting environment.
Additionally, at power-up the backlight compensation
zone, power-up condition, and direct A/D output modes
are selectable without IIC control by using the PUD pins.
Requiring a minimum of parts for operation, the CH5101
provides a low cost camera for the next generation
videophone, toy, and surveillance products.
Photocell
352
Columns
Array
288
Rows
Row Decode
R
O
W
T
I
M
I
N
G
Shutter
Control
Gain
A/D
Black
Clamp
201-0000-033 Rev 1.0, 6/2/99
2-D Gamma
LPF Correct
Figure 1: Block Diagram
I 2C
BUS
SD
SC
AS
Timing
&
Mode
Control
Output
Format
HREF
PDP*
HS*
VS*
CLKOUT
Reset*
XI/Fin
XO
PUD[6:0]
TOUT/TOUTB
OVR
Y[7:0]
1
3
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CH5101A
Table 1. Pin Descriptions Note: Pin numbers in parenthesis ( ) are for 52 pin PQFP
Pin
21-14
(14-7)
1,7,11,22,34,
(4,15,27,46,52)
4,8,24,36,
(1, 17, 29, 49)
Type
Out
Power
Power
Symbol
Y[7:0]
DVDD
DGND
31-25
(24-18)
In
PUD[5:0]*
PUD[6]
23 Out CLKOUT
(16)
9 Out VS*
(2)
10 Out HS*
(3)
12 Out OVR
(5)
13 Out HREF
(6)
6 In SC
(51)
5 In/Out SD
(50)
2 In AS
(47)
3 In
(48)
RESET*
38 In/Out XO
(31)
39 In
(32)
XI/FIN
Description
Video Output
Provides the luminance data of the digital video output.
Digital Supply Voltage
These pins supply the 5V power to the digital section of CH5101.
Digital Ground
Provides the ground reference for the digital section of CH5101. These
pins MUST be connected to the system ground.
Power Up Detect (internal pull-up)
These are inputs controlling the default value of IIC register bits
M0, ADDO, PD, ASW[3:0]. Attach 100K Ohms to DGND to pull low.
NOTE: PUD[5:0]* are logically inverted
Video Pixel Clock Output
This pin outputs a buffered clock signal which can be used to latch data
output by pins Y[7:0]
Vertical Sync Output (active low)
Outputs a vertical sync pulse.
Horizontal Sync Output (active low)
Outputs a horizontal sync pulse.
Over Range
This pin is high when the A/D converter input is beyond the full scale
range of the A/D.
Horizontal Reference
Active video timing signal. This output is high when active data is being
output from the device, and low otherwise.
Serial Clock
IIC clock input pin.
Serial Data
IIC data input/output pin.
Chip Address Select (internal pullup)
This pin selects the IIC address for the device.
AS = 1 Address = 100 0101
AS = 0 Address = 100 0110
Chip Reset (active low, internal pullup)
Puts all registers into power-on default states. The state at pin SD must
be HIGH during reset for proper initialization.
Crystal Output
A 27 MHz (± 50 ppm, parallel resonance) crystal may be attached
between XO and XI/FIN.
Crystal Input or External input
A 27 MHz (± 50 ppm, parallel resonance) crystal should be attached
between XO and XI/FIN. An external CMOS compatible clock can be
connected to XI/FIN as an alternative.
201-0000-033 Rev 1.0, 6/2/99
5
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CH5101A
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The RP limit depends on VDD and is shown below:
RP >= (100 x VDD)/ Iinput (where: RP is in kΩ and Iinput is in µA) Transfer Protocol
Both read and write cycles can be executed in Alternating and Auto-increment modes. Alternating mode expects a
register address prior to each read or write from that location (i.e., transfers alternate between address and data).
Auto-increment mode allows you to establish the initial register location, then automatically increments the register
address after each subsequent data access (i.e., transfers will be address, data, data, data...). A basic serial port
transfer protocol is shown in Figure 6 and described below.
SD
SC 1 - 7 8 9 1 - 8 9
Start
Condition
Device ID
R/W* ACK
CH5101
acknowledge
Data1
ACK
CH5101
acknowledge
1-8 9
Data n
ACK
CH5101
acknowledge
Stop
Condition
Figure 6: Serial Port Transfer Protocol
1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the
START condition. Transitions of address and data bits can only occur while SC is low.
2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the
STOP condition.
3. Upon receiving the first START condition, the CH5101 expects a Device Address Byte (DAB) from the
master device. The value of the device address is shown in the DAB data format below. Note that B[2:1] is
determined by the state of the ADDR pin (see Table 1 for details).
Table 3. Device Address Byte (DAB)
B7 B6 B5 B4 B3 B2 B1 B0
1 0 0 0 1 AS* AS R/W
4. After the DAB is received, the CH5101 expects a Register Address Byte (RAB) from the master. The
format of the RAB is shown in the RAB data format below (note that B7 is not used).
R/W Read/Write Indicator
0: Master device will write to the CH5101 at the register location specified by the address
AR[5:0]
1: Master device will read from the CH5101 at the register location specified by the
address AR[5:0]. AutoInc Register Address Auto-Increment - to facilitate sequential
R/W of registers 1: Auto-Increment enabled (auto-increment mode).
201-0000-033 Rev 1.0, 6/2/99
11
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| PDF Descargar | [ Datasheet CH5101A.PDF ] | |
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