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PDF NJU26123 Data sheet ( Hoja de datos )
| Número de pieza | NJU26123 | |
| Descripción | Digital Signal Processor | |
| Fabricantes | NJR Corporation | |
| Logotipo |  |
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NJU26123
Digital Signal Processor for TV
■ General Description
■Package
The NJU26123 is a high performance 24-bit digital signal processor.
The NJU26123 provides ‘NJRC Original Sound Enhancement’, ‘Lip sync Audio
Delay’, 10band PEQ, HPF/LPF (FIR Filter), DRC, Tone Control, and Clipper.
These kinds of sound functions are suitable for TV, mini-component, CD
radio-cassette, speakers system and other audio products.
■ FEATURES
NJU26123V
- Software
• NJRC Original Sound Enhancement (3D sound, Dialogue Boost, Bass Enhance)
• Delay for Lip sync Audio Delay
( fs=48kHz : Max. 36msec, fs=44.1kHz : Max. 39msec, fs=32kHz : Max. 54msec )
• 10Band PEQ
• HPF/LPF (FIR Filter)
• DRC (Dynamic Range Compression) : 2-bands independent operation
• Tone Control
• Clipper
• Master Volume
• WatchDog Clock Output
- Hardware
• 24bit Fixed-point Digital Signal Processing
• Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit
• Digital Audio Interface
: 3 Input ports / 3 Output ports
• Digital Audio Format
: I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs
• Master / Slave Mode
- Master Mode, MCK : 384fs @32kHz, 256fs @48kHz
• Host Interface
: I2C bus (Fast-mode/400kbps)
• Power Supply
: 3.3V
• Input terminal
: 5V Input tolerant
• Package
: SSOP24 (Pb-Free)
Ver.2008-04-17
-1-
1 page  
www.DataSheet4U.com
■ Absolute Maximum Ratings
NJU26123
Table 2 Absolute Maximum Ratings
Parameter
Symbol
( VSS=0V=GND, Ta=25°C )
Rating
Units
Supply Voltage *
Supply Voltage Bypass *
In
I/O, OD
Pin Voltage *
Out
CLK
VDD
VREGO
Vx(IN)
Vx(I/O) ,Vx(OD)
Vx(OUT)
Vx(CLK)
-0.3 to 4.2
-0.3 to 2.3
-0.3 to 5.5 (VDD≥ 3.0V)
-0.3 to 4.2 (VDD< 3.0V)
-0.3 to 4.2
V
V
V
CLKOUT Vx(CLKOUT)
Power Dissipation
Operating Voltage
Storage Temperature
PD
TOPR
TSTR
565
-40 to 85
-40 to 125
mW
°C
°C
* The LSI must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause permanent
damage to the LSI.
* VDD
* VREGO
* Vx(IN)
* Vx(OD)
* Vx(I/O)
* Vx(OUT)
* Vx(CLK)
* Vx(CLKOUT)
: 8 pin
: 12 pin
: 1, 4, 5, 6, 10, 15, 23, 24 pin
: 22 pin
: 2, 3, 7, 16, 17, 18 pin
: 19, 20, 21 pin
: 14 pin
: 13 pin
■ Terminal equivalent circuit diagram
VDD
VDD(1.8V)
CLK
CLKOUT
VDD
VDD(1.8V)
PAD
RPD
Input, I/O (Input part) VSS
(1 to 7, 22, 23pin)
(with RPU : 18pin , With RPD: 15, 16, 17, 24pin)
VDD
RPU
PAD
CLK/CLKOUT
(13, 14pin)
VSS
VDD
PAD
Output Disable
VSS
Output, I/O (Output part)
(2, 3, 7, 16, 17, 19, 20, 21pin )
( Open Drain Output with RPU: 18pin)
( Open Drain Output: 22pin )
STBYb
(10pin)
VSS
Fig.4 NJU26123 Terminal equivalent circuit diagram
Ver.2008-04-17
-5-
5 Page 
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3. Digital Audio Interface
NJU26123
3.1 Digital Audio Data Format
The NJU26123 can use three kinds of formats hereafter as industry-standard digital audio data format.
(1) I2S
: MSB is put on the 2nd bit of LR clock change rate.(1 bit is delayed to left stuffing)
(2) Left-justified : LR clock -- MSB is placed for changing.
(3) Right-justified : LSB is placed just before LR clock change rate.
The main differences among three kinds of formats are in the position relation between LR clock (LR) and
an audio data (SDI, SDO).
- In every format:
: a left channel is transmitted previously.
- In Right/Left-justified : LR clock ='High' shows a left channel.
- I2S : LR clock=”Low” shows a left channel.
- The Bit clock BCK is used as a shift clock of transmission data. The number of clocks more than
the number of sum total transmission bits of a L/R channel is needed at least.
- One cycle of LR clock is one sample of a stereo audio data. The frequency of LR clock becomes
equal to a sample rate (Fs).
- The NJU26123 supports serial data format which includes 32(32fs) or 64(64fs) BCK clocks.
This serial data format is applied to both MASTER and SLAVE mode.
3.2 Serial Audio Data Input/output
The NJU26123 audio interface includes 3 data input lines: SDI0, SDI1 and SDI2 (Table 8). 3 data output
lines: SDO0, SDO1 and SDO2. (Table 9).
Table 8 Serial Audio Input Pin Description
Pin No. Symbol
Description
6 SDI0 Audio Data Input 0 L/R
5 SDI1 Audio Data Input 1 L/R
4 SDI2 Audio Data Input 2 L/R
Table 9 Serial Audio Output Pin Description
Pin No. Symbol
Description
19 SDO0 Audio Data Output 0 L/R
20 SDO1 Audio Data Output 1 L/R
21 SDO2 Audio Data Output 2 L/R
Ver.2008-04-17
- 11 -
11 Page | ||
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| PDF Descargar | [ Datasheet NJU26123.PDF ] | |
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