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PDF NJU26124 Data sheet ( Hoja de datos )

Número de pieza NJU26124
Descripción Digital Signal Processor
Fabricantes NJR Corporation 
Logotipo NJR Corporation Logotipo



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NJU26124
Digital Signal Processor for TV
General Description
Package
The NJU26124 is a high performance 24-bit digital signal processor.
The NJU26124 provides 512TAP FIR Filter, PEQ and Time Alignment Delay.
These kinds of sound functions are suitable for TV, mini-component, CD
radio-cassette, speakers system and other audio products.
FEATURES
- Software
512TAP FIR Filter x 2 channels
PEQ : NJU26124 supports a multi channel product
2ch output : 26 Band / ch, 6ch output : 8 Band / ch
Either FIR Filter or PEQ is selected.
Filters : PEQ, LPF, HPF, LSF, HSF
Time Alignment Delay
Master Volume
WatchDog Clock Output
NJU26124VC2
- Hardware
24bit Fixed-point Digital Signal Processing
Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit
Digital Audio Interface
Digital Audio Format
: 3 Input ports / 3 Output ports
: I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs
Master / Slave Mode
- Master Mode, MCK : 384fs @32kHz, 256fs @48kHz
Host Interface
: I2C bus (Fast-mode/400kbps)
Power Supply
: 3.3V
Input terminal
: 5V Input tolerant
Package
: SSOP24-C2 (Pb-Free)
Ver.2008-12-03
-1-

1 page




NJU26124 pdf
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Fig. 2-5 PEQ + Time Alignment Delay Block Diagram Input : 2.1ch or 3ch
NJU26124
SDI0 L
SDI0 R
SDI1 C or SW
Input Trimmer
PEQ
17 Band
PEQ
17 Band
PEQ
17 Band
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Master Volume &
Channel Trimmer
SDO0 L
SDO0 R
SDO1 C or SW
SDI0 L
SDI0 R
SDI1 C or SW
Input Trimmer
PEQ
12 Band
PEQ
12 Band
PEQ
12 Band
PEQ
12 Band
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Master Volume &
Channel Trimmer
SDO0 L
SDO0 R
SDO1 C or SW
SDO1 C or SW
Fig. 2-5-1 Output : 2.1ch or 3ch
SDI0 L
SDI0 R
SDI1 C or SW
Input Trimmer
PEQ
10 Band
PEQ
10 Band
PEQ
10 Band
PEQ
10 Band
PEQ
10 Band
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Master Volume &
Channel Trimmer
Time Alignment
Delay
Time Alignment
Delay
SDO0 L
SDO0 R
SDO1 C or SW
SDO2 L for LS
SDO2 R for RS
Fig. 2-5-3 Output : 4.1ch or 5ch (2.1ch or 3ch)
Fig. 2-5-2 Output : 3.1ch
SDI0 L
SDI0 R
SDI1 C or SW
Input Trimmer
PEQ
8 Band
PEQ
8 Band
PEQ
8 Band
PEQ
8 Band
PEQ
8 Band
PEQ
8 Band
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Master Volume &
Channel Trimmer
SDO0 L
SDO0 R
SDO1 C or SW
SDO1 C or SW
SDO2 L for LS
SDO2 R for RS
Fig. 2-5-4 Output : 5.1ch (3.1ch)
Fig. 2-6 PEQ + Time Alignment Delay Block Diagram Input : 4ch
SDI0 L
SDI0 R
SDI2 LS
SDI2 RS
Input Trimmer
PEQ
12 Band
PEQ
12 Band
PEQ
12 Band
PEQ
12 Band
Time Alignment
Delay
Time Alignment
Delay
Master Volume &
Channel Trimmer
Time Alignment
Delay
Time Alignment
Delay
SDO0 L
SDO0 R
SDO2 LS
SDO2 RS
Fig. 2-6-1 Output : 4ch
SDI0 L
SDI0 R
SDI2 LS
SDI2 RS
Input Trimmer
PEQ
8 Band
PEQ
8 Band
PEQ
8 Band
PEQ
8 Band
PEQ
8 Band
PEQ
8 Band
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Master Volume &
Channel Trimmer
SDO0 L
SDO0 R
SDO1 C or SW
SDO1 C or SW
SDO2 LS
SDO2 RS
SDI0 L
SDI0 R
SDI2 LS
SDI2 RS
Input Trimmer
PEQ
10 Band
PEQ
10 Band
PEQ
10 Band
PEQ
10 Band
PEQ
10 Band
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Master Volume &
Channel Trimmer
Time Alignment
Delay
Time Alignment
Delay
SDO0 L
SDO0 R
SDO1 C or SW
SDO2 LS
SDO2 RS
Fig. 2-6-2 Output : 4.1ch or 5ch
SDI0 L
SDI0 R
SDI2 LS
SDI2 RS
Input Trimmer
PEQ
8 Band
PEQ
8 Band
PEQ
8 Band
PEQ
8 Band
PEQ
8 Band
PEQ
8 Band
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Time Alignment
Delay
Master Volume &
Channel Trimmer
SDO0 L
SDO0 R
SDO1 L
SDO1 R
SDO2 LS
SDO2 RS
Fig. 2-6-3 Output : 5.1ch
Fig. 2-6-4 Output : 6ch (4ch)
Ver.2008-12-03
-5-

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NJU26124 arduino
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1.4 Reset
NJU26124
To initialize the NJU26124, RESETb pin should be set Low level during some period. After some period of
Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26124. After
the power supply and the oscillation of the NJU26124 becomes stable, RESETb pin must be kept
Low-level more than tRESETb period. (Fig.5)
After RESETb pin level goes to "High" (after reset release), a setup of the internal hardware of a Serial
Host Interface completes NJU26124 within 10msec. Then, it will be in the state which can communicate.
VDD
VREGO
CLK
tVREGO
OSC unstable
OSC stable
RESETb
Fig. 5 Reset Timing
tRESETb
Table 4 Reset Time
Symbol
Time
tVREGO
tRESETb
10msec
1.0msec
Note :
Don’t stop the supply of a clock while operating. NJU26124 installs PLL circuit internally. If the supply of a
clock is stopped, PLL circuit cannot be sent a clock to the inside and NJU26124 does not operate normally.
If supply of a clock is stopped or the NJU26124 is reset again, putting a normal clock into CLK terminal, the
period RESETb terminal of tRESETb is kept “Low” level.(Table 4) Next, the NJU26124 is reset. Then redo
from initial setting.
Ver.2008-12-03
- 11 -

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