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PDF DS64EV400 Data sheet ( Hoja de datos )
| Número de pieza | DS64EV400 | |
| Descripción | Programmable Quad Equalizer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
April 18, 2008
DS64EV400
Programmable Quad Equalizer
General Description
The DS64EV400 programmable quad equalizer provides
compensation for transmission medium losses and reduces
the medium-induced deterministic jitter for four NRZ data
channels. The DS64EV400 is optimized for operation up to
10 Gbps for both cables and FR4 traces. Each equalizer
channel has eight levels of input equalization that can be pro-
grammed by three control pins, or individually through a Serial
Management Bus (SMBus) interface.
The equalizer supports both AC and DC-coupled data paths
for long run length data patterns such as PRBS-31, and bal-
anced codes such as 8b/10b. The device uses differential
current-mode logic (CML) inputs and outputs. The
DS64EV400 is available in a 7 mm x 7 mm 48-pin leadless
LLP package. Power is supplied from either a 2.5V or 3.3V
supply.
Features
■ Equalizes up to 24 dB loss at 10 Gbps
■ Equalizes up to 22 dB loss at 6.4 Gbps
■ 8 levels of programmable equalization
■ Settable through control pins or SMBus interface
■ Operates up to 10 Gbps with 30” FR4 traces
■ Operates up to 6.4 Gbps with 40” FR4 traces
■ 0.175 UI residual deterministic jitter at 6.4 Gbps with 40”
FR4 traces
■ Single 2.5V or 3.3V power supply
■ Signal Detect for individual channels
■ Standby mode for individual channels
■ Supports AC or DC-Coupling with wide input common-
mode
■ Low power consumption: 375 mW Typ at 2.5V
■ Small 7 mm x 7 mm 48-pin LLP package
■ 9 kV HBM ESD Rating
■ -40 to 85°C operating temperature range
Simplified Application Diagram
© 2008 National Semiconductor Corporation 300320
30032024
www.national.com
1 page  
wwSwy.DmabtaoSl heet4U.com Parameter
CML RECEIVER INPUTS (IN_n+, IN_n-)
VTX Source Transmit Launch Signal
Level (IN diff)
VINTRE
VDDTX
VICMDC
Input Threshold Voltage
Supply Voltage of Transmitter to
EQ
Input Common Mode Voltage
RLI Differential Input Return Loss
RIN Input Resistance
CML OUTPUTS (OUT_n+, OUT_n-)
VOD Output Differential Voltage Level
(OUT diff)
VOCM
Output Common Mode Voltage
tR, tF
Transition Time
RO Output Resistance
RLO Differential Output Return Loss
tPLHD
tPHLD
tCCSK
tPPSK
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Inter Pair Channel to Channel
Skew
Part to Part Output Skew
EQUALIZATION
DJ1 Residual Deterministic Jitter
at 10 Gbps
DJ2 Residual Deterministic Jitter
at 6.4 Gbps
DJ3 Residual Deterministic Jitter
at 5 Gbps
DJ4 Residual Deterministic Jitter
at 2.5 Gbps
RJ Random Jitter
Conditions
Min
AC-Coupled or DC-Coupled
Requirement, Differential
measurement at point A.
Figure 1
Differential measurement at
point B. Figure 1
DC-Coupled Requirement
(Note 10)
DC-Coupled Requirement,
Differential measurement at point
A. Figure 1, (Note 7)
100 MHz – 3.2 GHz, with fixture’s
effect de-embedded
Differential across IN+ and IN-,
Figure 6.
400
1.6
VDDTX –
0.8
85
Differential measurement with
OUT+ and OUT- terminated by
50Ω to GND, AC-Coupled
Figure 2
Single-ended measurement DC-
Coupled with 50Ω terminations
(Note 7)
20% to 80% of differential output
voltage, measured within 1” from
output pins. Figure 2, (Note 7)
Single ended to VDD
100 MHz – 1.6 GHz, with fixture’s
effect de-embedded. IN+ = static
high.
Propagation delay measurement
at 50% VO between input to
output, 100 Mbps. Figure 3,
(Note 7)
Difference in 50% crossing
between channels
Difference in 50% crossing
between outputs
500
VDD– 0.2
20
42
30” of 6 mil microstrip FR4,
EQ Setting 0x06, PRBS-7 (27-1)
pattern. (Note 6)
40” of 6 mil microstrip FR4,
EQ Setting 0x06, PRBS-7 (27-1)
pattern. (Note 5, 6)
40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (27-1)
pattern. (Note 5, 6)
40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (27-1)
pattern. (Note 5, 6)
(Note 7, 8)
Typ
(note 2)
120
10
100
620
50
10
240
240
7
20
0.20
0.17
0.12
0.1
0.5
Max
1600
VDD
VDDTX –
0.2
115
725
VDD– 0.1
60
58
0.26
0.20
0.16
Units
mVP-P
mVP-P
V
V
dB
Ω
mVP-P
V
ps
Ω
dB
ps
ps
ps
ps
UIP-P
UIP-P
UIP-P
UIP-P
psrms
5 www.national.com
5 Page 
www.DataSheet4U.com
30032005
FIGURE 5. Enable (EN) Delay Timing Diagram
300320017
FIGURE 6. Simplified Receiver Input Termination Circuit
FIGURE 7. SMBus Timing Parameters
300320018
11 www.national.com
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet DS64EV400.PDF ] | |
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