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PDF DS64EV100 Data sheet ( Hoja de datos )
| Número de pieza | DS64EV100 | |
| Descripción | Programmable Single Equalizer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 9, 2007
DS64EV100
Programmable Single Equalizer
General Description
The DS64EV100 programmable equalizer provides compen-
sation for transmission medium losses and reduces the medi-
um-induced deterministic jitter for NRZ data channel. The
DS64EV100 is optimized for operation up to 10 Gbps for both
cables and FR4 traces. The equalizer channel has eight lev-
els of input equalization that can be programmed by three
control pins.
The equalizer supports both AC and DC-coupled data paths
for long run length data patterns such as PRBS-31, and bal-
anced codes such as 8b/10b. The device uses differential
current-mode logic (CML) inputs and outputs, and is available
in a 3 mm x 4 mm 14-pin leadless LLP package. Power is
supplied from either a 2.5V or 3.3V supply.
Features
■ Equalizes up to 24 dB loss at 10 Gbps
■ Equalizes up to 22 dB loss at 6.4 Gbps
■ 8 levels of programmable equalization
■ Operates up to 10 Gbps with 30” FR4 traces
■ Operates up to 6.4 Gbps with 40” FR4 traces
■ 0.175 UI residual deterministic jitter at 6.4 Gbps with 40”
FR4 traces
■ Single 2.5V or 3.3V power supply
■ Supports AC or DC-Coupling with wide input common-
mode
■ Low power consumption: 100 mW Typ at 2.5V
■ Small 3 mm x 4 mm 14-pin LLP package
■ >8 kV HBM ESD
■ -40 to 85°C operating temperature range
Simplified Application Diagram
© 2007 National Semiconductor Corporation 201964
20196401
www.national.com
1 page  
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FIGURE 1. Test Setup Diagram
20196403
FIGURE 2. CML Output Transition Times
20196404
FIGURE 3. Propagation Delay Timing Diagram
20196405
5 www.national.com
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet DS64EV100.PDF ] | |
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