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PDF CDRM622 Data sheet ( Hoja de datos )

Número de pieza CDRM622
Descripción 622 Mbits/s Multichannel Digital Timing Recovery
Fabricantes Agere Systems 
Logotipo Agere Systems Logotipo



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No Preview Available ! CDRM622 Hoja de datos, Descripción, Manual

Data Sheet
June 1999
www.DataSheet4U.com
CDRM622
622 Mbits/s Multichannel Digital Timing Recovery
Features
s Receives scrambled serial data at STS-12/STM-4
(622.08 Mbits/s) rate.
s Demultiplexes serial data to 77.76 Mbytes/s paral-
lel byte wide data with aligned 77.76 MHz clock.
s Synthesizes 622.06 MHz clock with on-chip PLL,
requiring only 77.76 MHz input reference clock and
one external resistor.
s Multiplexes parallel 77.76 Mbytes/s data to
622 Mbits/s serial data for transmission.
s Incorporates n = 1 to 16 channels with modular
design. Implemented in Lucent Technologies
Microelectronics Group HL250C technology.
s Meets type B jitter tolerance specification of ITU-T
Recommendation G.958.
s Sources stable clock in absence of data transitions
once the clock synthesizer has acquired lock.
s Uses single, low-voltage (3.3 V ± 5%) supply.
s Includes built-in test circuitry such as high-speed
loopback of transmit data into receiver.
s IDDQ compatible.
s Powers down the receiver on per-channel basis.
s Allows JTAG access to high-speed data paths.
Description
The CDRM622 provides a physical medium for high-
speed asynchronous serial data transfer between
ASIC devices. Devices can be on the same PC-
board, or on separate boards connected across a
backplane, or connected by cables. The macrocell is
intended for, but not limited to, terminal equipment in
SONET/SDH and ATM systems.
The macrocell consists of three functional blocks.
The receiver accepts 622.08 Mbits/s serial data.
Based on data transitions, the receiver selects an
appropriate 622 MHz clock phase for each channel
to retime the data, then demultiplexes down to
77.76 Mbytes/s parallel bytes and a 77.76 MHz clock.
The transmitter operates in the reverse direction.
77.76 Mbytes/s parallel bytes are multiplexed up to
662.08 Mbits/s serial data for off-chip communica-
tion.
The clock synthesizer generates the necessary
622.08 MHz clock for operation from a 77.76 MHz
reference. Figure 1 illustrates the function of the mac-
rocell.
The hard macrocell can be supplied for up to 16 data
channels. Multiple macrocells can be used on a sin-
gle device. The macrocell is intended to be used with
high-speed differential I/O buffers for the 622 Mbits/s
serial data streams and the 77.76 MHz reference
clock. Common selections are low-voltage differential
swing (LVDS) or PECL. The I/O buffers are part of
our standard-cell ASIC library and are not included in
the macrocell to allow for flexibility.

1 page




CDRM622 pdf
Data Sheet
June 1999
CDRM622
622 Mbits/s Multichannel Digital Timing Recovery Macrocell
www.DataSheet4U.com
Hardware Interface (continued)
CLOCK SYNTHESIZER
PHASE
ERROR
DETECTOR
CDRM622
OUTPUT DATA
RELATIVE TO OUTPUT CLOCK
±1.0 ns
RECEIVER
byte
Q
S
CK/8
78 MHz
S
622 MHz
STDCELLS
(TEST LOGIC)
78
MHz
CK/8
D
TRANSMITTER
S
S
D
INVERT CLOCK
TO USE
POSITIVE EDGE
FLIP-FLOP
byte
Q
LCK78
REF78
78 MHz
INPUT DATA SETUP/HOLD
1.9 ns/0.2 ns
Figure 2. 78 MHz Interfaces
PLL REFERENCE
CLOCK
5-7714(F)r.2
Lucent Technologies Inc.
5

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CDRM622 arduino
Data Sheet
June 1999
CDRM622
622 Mbits/s Multichannel Digital Timing Recovery Macrocell
www.DataSheet4U.com
Electrical and Timing Characteristics
Table 5. Absolute Maximum Ratings
Parameter
Power Dissipation
Conditions
16 channels at 3.3 V
1. At 3.3 V, power is estimated by 300 mW + 50 mW per Rx channel + 10 mW per Tx channel.
Min
Typ Max Unit
— 1.251 W
Table 6. Recommended Operating Conditions
Parameter
Supply Voltage
Conditions
Min Typ Max Unit
3.135
3.465
V
Table 7. Receiver Specifications
Parameter
Conditions
Min Typ Max Unit
Input Data1
Stream of Nontransitional 622 Mbits/s2
— — 60 bits
Phase Change, Input Signal
Over a 200 ns time interval3
— 100 ps
Eye Opening4
0.4 —
— UIp-p
Jitter Tolerance
Jitter Tolerance:
250 kHz
25 kHz
2 kHz
— — 0.6 UIp-p
——
6 UIp-p
— — 60 UIp-p
1. 622 Mbits/s scrambled data stream conforming to SONET STS-12 and SDH STM-4 data format using either a PN7 or PN9 sequence.
s PN7 charateristic is 1 + x6 + x7.
s PN9 charateristic is 1 + x4 + x9.
2. This sequence should not occur more than once per minute.
3. Translates to a frequency change of 500 ppm.
4. A unit interval for 622 Mbits/s data is 1.6075 ns.
Table 8. Transmitter Specifications
Parameter
Output Jitter, Generated
Conditions
250 kHz to 5 MHz (measured
with a spectrum analyzer)
Min
Typ Max Unit
— 0.2 UIp-p
Table 9. Synthesizer Specifications
PLL1
Parameter
Loop Bandwidth
Jitter Peaking
Powerup Reset Time
Lock Aquisition Time
Input Reference Clock
Frequency
Frequency Deviation
Phase Change
Conditions
Over a 200 ns time interval2
1. External 10 kresistor to analog ground required.
2. Translates to a frequency change of 500 ppm.
Min
10
77.76
Typ
Max
6
2
1
±20
100
Unit
MHz
dB
µs
ms
MHz
ppm
ps
Lucent Technologies Inc.
11

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