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PDF LF3370 Data sheet ( Hoja de datos )
| Número de pieza | LF3370 | |
| Descripción | High-Definition Video Format Converter | |
| Fabricantes | LOGIC Devices Incorporated | |
| Logotipo |  |
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DEVICES INCORPORATED
DEVICES INCORPORATED
LF3370
LF3370High-Definition Video Format Converter
High-Definition Video Format Converter
FEATURES
DESCRIPTION
u 83 MHz Data Rate for HDTV
Applications
u Supports Multiple Video Formats
Bi-Directional Conversions:
- 4:2:2:4
- 4:4:4:4
- R/G/B/Key
- Y/U/V/Key
u Multiplexed and Non-multiplexed
I/O Data
u User-Programmable:
- 3 x 3 Colorspace Converter
- LUT for Gamma Correction
- I/O Bias Compensation
- Bypass Capability
u 13-bit Data Path, Colorspace
Converter Coefficients and Key
Channel Scaling Coefficients
u 160-lead PQFP
LF3370 BLOCK DIAGRAM
A12-0
B12-0
The LF3370 is a video format
converter capable of operating at
HDTV data rates. This device
converts to and from any of the
various SDTV/HDTV digital video
formats by utilizing an internal
3 x 3 Matrix Multiplier and two
1:2 Interpolation/2:1 Decimation
Half-Band Filters.
Using the Input Demultiplexer
and Output Multiplexer, the
LF3370 can accept and output
interleaved or non-interleaved
video. For example, R/G/B/Key
data can be color space converted
to Y/U/V/Key and down-con-
verted to 4:2:2:4. By re-arranging
the order of the functional sec-
tions, the opposite conversion can
be achieved. The coefficients for
C12-0
D12-0
INPUT DE-MULTIPLEXER SECTION
INPUT BIAS ADDERS
the 3 x 3 Matrix Multiplier are
fully user programmable to sup-
port a wide range of color space
conversions. The two Interpola-
tion/Decimation Half-Band Filters
are fully compliant with SMPTE
260M.
Input and Output Bias Adders are
included for removing or adding a
user-defined bias into the video
signal. In addition, three pro-
grammable 1K x 13-bit Look-Up
Tables (LUTs) have also been
included for various uses such as
gamma correction. A Scaler has
been included on the Key Channel
for scaling to a desired magnitude
using user programmable coeffi-
cients.
Input signals can also be forced to
user-defined levels for horizontal
blanking. Furthermore, Round/
Select/Limit (RSL) circuitry is
provided at the end of various
stages to provide the best possible
conversions without color viola-
tions. For additional flexibility,
the Halfband Filter can be indi-
vidually bypassed using an inter-
nal programmable length delay.
All control and coefficient registers
are loaded through the LF Inter-
face™.
COLORSPACE
CONVERTER/
KEY SCALER
55-TAP HALF-BAND
INTERPOLATION/
DECIMATION
FILTERS
1K x 13-Bit
LOOK-UP-TABLES
This device operates at 3.3 V (5 V
tolerant I/O) and is available in
160-lead PQFP package.
OUTPUT BIAS ADDERS
OUTPUT MULTIPLEXER SECTION
W12-0
X12-0
Y12-0
Z12-0
1
Video Imaging Products
03/13/2001–LDS.3370-F
1 page  
DEVICES INCORPORATED
LF3370
High-Definition Video Format Converter
on the rising edge of CLK.
RESET — Reset
RESET is used to reset all program-
mable flags and line up clock edges
during single muxed input or single
muxed output events. RESET is used
at power up or just after device
configuration. This pin is latched on
the rising edge of CLK.
LF3370DeviceInitialization
This section explains how to initialize the
deviceforproperoperation. Italsoservesas
a summary of all conditions that should be
consideredbeforeusingthedeviceorfor
troubleshooting.
TABLE 1. INPUT/OUTPUT FORMATS
Input
Channel
4:4:4:4
Input Format*
4:2:2:4
4:2:2:4
A12-0
B12-0
C12-0
D12-0
Output
Channel
R
G
B
Key
4:4:4:4
YY
Cb Cb/Cr
Cr N/A
Key Key
Output Format*
4:2:2:4
4:2:2:4
W12-0
X12-0
Y12-0
Z12-0
R
G
B
Key
YY
Cb Cb/Cr
Cr N/A
Key Key
4:2:2:4
Y/Cb/Cr
N/A
N/A
Key
4:2:2:4
Y/Cb/Cr
N/A
N/A
Key
* Not all input/output combinations are valid. If single channel interleaved video
is used on either the input or output, the core clock will be running at CLK/2.
Thus the maximum input, output, and core data rate must be considered.
Configuration Register 0 and Configuration
Register1mustbeloadedbeforeoperation
ofthedevice. IfCoreBypassingisdesired,
ConfigurationRegister2mustbeloaded
beforeuse. IfuseoftheHalf-BandFiltersis
desired, at least one Half-Band Filter RSL
Register Set must be loaded and selected for
each Half-Band Filter.
If use of the Matrix Multiplier/Key Scaler is
desired,atleastoneMatrixMultiplier/Key
Scaler RSL Register Set and coefficient
address mustbeloadedandselectedfor
each channel. If use of the Input Bias Adder
is desired, at least one Input Bias Adder
Registermustbeloadedandselectedbefore
use. IfuseoftheOutputBiasAdderis
desired, at least one Output Bias Adder
Registermustbeloadedandselectedbefore
use. IfuseoftheLook-UpTableisdesired,
theLook-UpTablemustbeloadedbefore
use.
When using a single channel input or
output with interleaved video, SYNC and
RESET should be used for proper initializa-
tion as shown in Figure 5. If 12 bits or less
input data is desired, the input data should
be shifted so the MSBs are aligned.
FIGURE 3. INPUT AND OUTPUT FORMATS
INPUT BIAS ADDER/OUTPUT BIAS ADDER
Input Data
Output Data
12 11 10
–212 211 210
(Sign)
210
22 21 20
12 11 10
–212 211 210
(Sign)
210
22 21 20
MATRIX MULTIPLIER/KEY SCALER
Input Data
Coefficient Data
12 11 10
–212 211 210
(Sign)
210
22 21 20
*Matrix Multiplier Output
12 11 10
–20 2–1 2–2
(Sign)
210
2–10 2–11 2–12
*Key Scaler Output
F19 F18 F17
–215 214 213
(Sign)
F2 F1 F0
2–2 2–3 2–4
F19 F18 F17
–213 212 211
(Sign)
F2 F1 F0
2–4 2–5 2–6
*Format of Matrix Multiplier/Key Scaler ouput feeding the RSL Circuitry. F19-F0 corresponds to 20 MSBs of which a
13-bit window can be selected from F19-F4 .
HALF-BAND FILTER
Input Data
12 11 10
–212 211 210
(Sign)
210
22 21 20
**Filter Output (Non-Interpolate)
**Filter Output (Interpolate)
Input Demultiplexer
The input demultiplexer section acts as a
buffer between the user’s datapath and the
F19 F18 F17
–212 211 210
(Sign)
F2 F1 F0
2–5 2–6 2–7
F19 F18 F17
–213 212 211
(Sign)
F2 F1 F0
2–4 2–5 2–6
*Format of Half-Band Filter ouput feeding the RSL Circuitry. F19-F0 corresponds to 20 MSBs of which a
13-bit window can be selected from F19-F4 (see Table 3).
Video Imaging Products
5 03/13/2001–LDS.3370-F
5 Page 
DEVICES INCORPORATED
LF3370
High-Definition Video Format Converter
FIGURE 13. RSL CIRCUITRY
corresponding output peak is 35 clock
cycles.
RSL1-0
2
R3
R0 S3
UL3
S0 LL3
UL0
LL0
From Core
20
20
20
ROUND
13
13
SELECT
13
LIMIT
13
13
TABLE 2. SELECT FORMATS
SLCT1-0 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
00 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4
01 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5
10 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6
11 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7
plier by setting bit 4 in Configuration
Register 0 (see Table 5). The maximum
input and output clock rate this section
can operate at is the CLK rate. The total
internal pipeline latency from the input to
the output of this section (including RSL
circuitry) as shown in Figure 12 is 6 cycles.
To perform interpolation, the input data
rate of this section will be half of CLK rate.
Please note the maximum output data
rateistheCLKrate. Toperformdecima-
tion, the output data rate of this section
will be half of the input data rate. One
output sample is obtained for every two
input samples.
Once an impulse is clocked into the Half-
Band Filter section, the 55-value output
response begins after 8 clock cycles and
ends after 62 clock cycles. The pipeline
latency from the input of an impulse to its
The input/output formats are always in
two’s complement format as shown in
Figure 3. In Interpolate Mode, the gain of
the Half-Band Filter is halved (due to half
of the input samples being padded with
zeros). A right shifted Select window is
required to maintain an overall filter gain
of 1. It is possible that ringing on the
filter’s output could cause the high order
bit (bit F18 in Figure 3 - Interpolate Filter
OutputBitWeighting)tobecomeHIGH. If
a right shifted Select window is used, this
F18 bit becomes the sign bit of the Selected
window – and the output is erroneously
considered negative. To ensure that no
overflow conditions occur, an internal
Limiter within each Half-Band Filter
monitorsitsoutput. DuringInterpolate
mode, this Limiter clamps the output word
to3FFFFH(20-bitmaximumpositivevalue
) 2) or C0000H (20-bit maximum negative
value) 2)ifapositiveornegativeoverflow
occurs respectively. The internal 24-bits of
the Half-Band Filter are truncated to 20-
bits and then passed to the Round section
of the RSL circuitry; see RSL section for
further details. This section is fully
bypassablebyuseofprogrammable
delays (see Bypass Options section for
furtherdetails).
FIGURE 14. FREQUENCY RESPONSE OF FILTER
0
–10
–20
–30
–40
–50
–60
–70
–80
0
0.1ƒS
0.2ƒS
0.3ƒS
0.4ƒS
0.5ƒS
Look-UpTable
ThreeoptionalprogrammableInput/
Output 1K x 13-bit LUTs have been
provided for Channels A, B, and C for
various uses such as Gamma Correction.
There are NOT actually two LUTs per
channel as shown in Figures 1 and 2; only
one LUT per channel can be selected for
use at any given time. The latency
through a LUT section is 2 cycles. This
latency is present on the datapath regard-
less of whether the LUT is in use or not.
When using a LUT, the appropriate
addressed value will be passed as an
FREQUENCY (NORMALIZED)
Video Imaging Products
11 03/13/2001–LDS.3370-F
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LF3370.PDF ] | |
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