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PDF LF3338 Data sheet ( Hoja de datos )

Número de pieza LF3338
Descripción 8-Bit Vertical Digital Image Filter
Fabricantes LOGIC Devices Incorporated 
Logotipo LOGIC Devices Incorporated Logotipo



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DEVICES INCORPORATED
DEVICES INCORPORATED
LF3338
LF33388-Bit Vertical Digital Image Filter
8-Bit Vertical Digital Image Filter
FEATURES
DESCRIPTION
u 83 MHz Data Rate
u 8-bit Data and 12-bit Coefficients
u Supports Interleaved Data Streams
u Cascadable for More Filter Taps
u Seven 3K x 8-bit, Dynamic Program-
mable Two-Mode Line Buffers
u On-board Memory for 256
Coefficient Sets
u LF InterfaceTM Allows All 256
Coefficient Sets to be Updated
Within Vertical Blanking
u Selectable 16-bit Data Output with
User-Defined Rounding and
Limiting
u Separate Input Port for Odd and
Even Field Filtering
u 8 Filter Taps
u 3.3 Volt Power Supply
u 5 Volt Tolerant I/O
u Purchase Description
The LF3338 is a lower cost version of
the 12-bit LF3330 and is suited for
multimedia and special effects systems,
projectors, plasma display panels, scan
converters, set-top boxes, and other
consumer applications.
This device filters digital images in
the vertical dimension at real-time
video rates. Input data is 8 bits and
coefficient data is 12 bits and both are
in two’s complement format. The
output is also in two’s complement
format and may be rounded to 16 bits.
The filter is an 8-tap FIR filter with all
required line buffers contained on-
chip. The line buffers can store video
lines with lengths from 4 to 3076
pixels. Multiple LF3338s can be
cascaded together to create larger
vertical filters.
Due to the length of the line buffers,
interleaved data can be fed directly
into the device and filtered without
separating the data into individual
data streams. The number of inter-
leaved data sets that the device can
handle is limited only by the length of
the on-chip line buffers. If the inter-
leaved video line has 3076 data values
or less, the filter can handle it.
The LF3338 contains enough on-board
memory to store 256 coefficient sets.
The LF InterfaceTM allows all 256
coefficient sets to be updated within
vertical blanking.
Selectable 16-bit data output with
user-defined rounding and limiting
minimizes the constraints put on
coefficient sets for various filter
implementations.
LF3338 BLOCK DIAGRAM
DIN7-0
8
3K LINE BUFFER
3K LINE BUFFER
VB7-0
8
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
ROUND
32 SELECT
LIMIT
CIRCUITRY
16
DOUT15-0
OED
3K LINE BUFFER
3K LINE BUFFER
8
COUT7-0
OEC
Video Imaging Products
1 04/06/1999–LDS.3338-B

1 page




LF3338 pdf
DEVICES INCORPORATED
LF3338
8-Bit Vertical Digital Image Filter
FUNCTIONAL DESCRIPTION
Line Buffers
The maximum delay length of each line
buffer is 3076 cycles and the minimum
is 4 cycles. Configuration Register 0
(CR0) determines the delay length of
the line buffers. The line buffer length
is equal to the value of CR0 plus 4. A
value of 0 for CR0 sets the line buffer
length to 4. A value of 3072 for CR0
sets the line buffer length to 3076. Any
values for CR0 greater than 3072 are not
valid.
The line buffers have two modes of
operation: delay mode and recirculate
mode. Bit 0 of Configuration Register 1
determines which mode the line buffers
are in. In delay mode, the data input to
the line buffer is delayed by an amount
determined by CR0. In recirculate
mode, the output of the line buffer is
routed back to the input of the line
buffer allowing the line buffer contents
to be read multiple times.
Bit 1 of Configuration Register 1 allows
the line buffers to be loaded in parallel.
When Bit 1 is “1”, the input register
(DIN7-0) loads all seven line buffers in
parallel. This allows all the line buffers
to be preloaded with data in the
amount of time it normally takes to
load a single line buffer.
Odd and Even Field Filtering
The LF3338 is capable of odd and even
field filtering. Bit 2 of Configuration
Register 1 enables the VB Data Input
port required for odd and even field
filtering. Bit 3 of the same configura-
tion register enables the line buffer in
the VB Data path. Line buffer length is
set to the length written to Configura-
tion Register 0. If line buffer parallel
load is enabled and odd and even field
filtering is enabled, the data for the VB
line buffer comes from the VB Data
Input port.
Interleaved Data
The LF3338 is capable of handling
interleaved data. The number of data
sets it can handle is determined by the
number of data values contained in a
video line. If the interleaved video line
has 3076 data values or less, the LF3338
can handle it no matter how many data
sets are interleaved together.
Cascading
A cascade port is provided to allow
cascading of multiple devices for
more filter taps (see Figure 5).
COUT7-0 of one device should be
connected to DIN7-0 of another
device. As many LF3338s as desired
may be cascaded together. How-
ever, the outputs of the LF3338s
must be added together with exter-
nal adders.
The first line buffer on a cascaded
device must have its length short-
ened by two delays. This is to
account for the added delays of the
input register on the device and the
cascade output register from the
previous LF3338. If Bit 0 of Con-
figuration Register 3 is set to “1”,
the length of the first line buffer will
be reduced by two. This will make
its effective length the same as the
other line buffers on the device. If
Bit 0 of Configuration Register 3 is
set to “0”, the length of the first line
buffer will be the same as the other
line buffers. When cascading
devices, the first LF3338 should
have Bit 0 of Configuration Register
FIGURE 5.
8
DIN
MULTIPLE LF3338S CASCADED TOGETHER
LF3338
LF3338
LINE BUFFERS
COUT
DIN
LINE BUFFERS
COUT
DIN
LF3338
LINE BUFFERS
COUT
DIN
LF3338
LINE BUFFERS
VERTICAL FILTER
RSL
CIRCUIT
VERTICAL FILTER
RSL
CIRCUIT
VERTICAL FILTER
RSL
CIRCUIT
VERTICAL FILTER
RSL
CIRCUIT
LF3347
25 25
RSL
CIRCUIT
16
DATA OUT
29 TAP RESULT
5
Video Imaging Products
04/06/1999–LDS.3338-B

5 Page





LF3338 arduino
DEVICES INCORPORATED
LF3338
8-Bit Vertical Digital Image Filter
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +4.5 V
Input signal with respect to ground .......................................................................................... –0.5 V to 5.5 V
Signal applied to high impedance output ................................................................................. –0.5 V to 5.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
ESD Classification (MIL-STD-883E METHOD 3015.7) ...................................................................... Class 3
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Active Operation, Military
Temperature Range (Ambient)
0°C to +70°C
–55°C to +125°C
Supply Voltage
3.00 V VCC 3.60 V
3.00 V VCC 3.60 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol Parameter
Test Condition
VOH Output High Voltage
VCC = Min., IOH = –4 mA
VOL Output Low Voltage
VCC = Min., IOL = 8.0 mA
VIH Input High Voltage
VIL Input Low Voltage
(Note 3)
IIX Input Current
Ground VIN VCC (Note 12)
IOZ Output Leakage Current Ground VOUT VCC (Note 12)
ICC1 VCC Current, Dynamic
(Notes 5, 6)
ICC2 VCC Current, Quiescent (Note 7)
CIN Input Capacitance
TA = 25°C, f = 1 MHz
COUT Output Capacitance
TA = 25°C, f = 1 MHz
Min Typ Max Unit
2.4 V
0.4 V
2.0 5.5 V
0.0 0.8 V
±10 µA
±10 µA
120 mA
1 mA
10 pF
10 pF
Video Imaging Products
11 04/06/1999–LDS.3338-B

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