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PDF LF3310 Data sheet ( Hoja de datos )

Número de pieza LF3310
Descripción Horizontal / Vertical Digital Image Filter
Fabricantes LOGIC Devices Incorporated 
Logotipo LOGIC Devices Incorporated Logotipo



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DEVICES INCORPORATED
DEVICES INCORPORATED
LF3310
LF3310Horizontal / Vertical Digital Image Filter
Horizontal / Vertical Digital Image Filter
FEATURES
DESCRIPTION
u 83 MHz Data Rate
u 12-bit Data and Coefficients
u On-board Memory for 256 Horizontal
and Vertical Coefficient Sets
u LF InterfaceTM Allows All 512
Coefficient Sets to be Updated
Within Vertical Blanking
u Selectable 12-bit Data Output with
User-Defined Rounding and
Limiting
u Seven 3K x 12-bit, Programmable
Two-Mode Line Buffers
u 16 Horizontal Filter Taps
u 8 Vertical Filter Taps
u Two Operating Modes: Dimension-
ally Separate and Orthogonal
u Supports Interleaved Data Streams
u Horizontal Filter Supports Decima-
tion up to 16:1 for Increasing
Number of Filter Taps
u 3.3 Volt Power Supply
u 5 Volt Tolerant I/O
u 144 Lead PQFP
The LF3310 is a two-dimensional digital
image filter capable of filtering data at
real-time video rates. The device
contains both a horizontal and a
vertical filter which may be cascaded or
used concurrently for two-dimensional
filtering. The input, coefficient, and
output data are all 12-bits and in two’s
complement format.
The horizontal filter is designed to take
advantage of symmetric coefficient sets.
When symmetric coefficient sets are
used, the horizontal filter can be
configured as a 16-tap FIR filter. When
asymmetric coefficient sets are used, it
can be configured as an 8-tap FIR filter.
The vertical filter is an 8-tap FIR filter
with all required line buffers contained
on-chip. The line buffers can store
video lines with lengths from 4 to 3076
pixels.
Horizontal filter Interleave/Decima-
tion Registers (I/D Registers) and the
vertical filter line buffers allow
interleaved data to be fed directly into
the device and filtered without
separating the data into individual
data streams. The horizontal filter
can handle a maximum of sixteen
data sets interleaved together. The
vertical filter can handle interleaved
video lines which contain 3076 or less
data values. The I/D Registers and
horizontal accumulator facilitate
using decimation to increase the
number of filter taps in the horizontal
filter. Decimation of up to 16:1 is
supported.
The device has on-chip storage for 256
horizontal coefficient sets and 256
vertical coefficient sets. Each filter’s
coefficients are loaded independently
of each other allowing one filter’s
coefficients to be updated without
affecting the other filter’s coefficients.
In addition, a horizontal or vertical
coefficient set can be updated inde-
pendently from the other coefficient
sets in the same filter.
LF3310 BLOCK DIAGRAM
DIN11-0
12
16-TAP HORIZONTAL FILTER
256 COEFFICIENT SET STORAGE
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
1
12
DOUT11-0
Video Imaging Products
11/08/2001-LDS.3310-H

1 page




LF3310 pdf
DEVICES INCORPORATED
LF3310
Horizontal / Vertical Digital Image Filter
HRSL3-0 — Horizontal Round/Select/
Limit Control
HRSL3-0 determines which of the
sixteen user-programmable Round/
Select/Limit registers (RSL registers)
are used in the horizontal Round/
Select/Limit circuitry (RSL circuitry).
A value of 0 on HRSL3-0 selects
RSL register 0. A value of 1 selects
round/select/limit register 1 and so
on. HRSL3-0 is latched on the rising
edge of CLK (see the horizontal
round, select, and limit sections for a
complete discussion).
FIGURE 4. DIMENSIONALLY SEPARATE MODE: H TO V
DIN11-0
12
HORIZONTAL FILTER
12
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
12
DOUT11-0
VRSL3-0 —Vertical Round/Select/Limit
Control
VRSL3-0 determines which of the
sixteen user-programmable
RSL registers are used in the vertical
RSL circuitry. A value of 0 on
VRSL3-0 selects RSL register 0. A
value of 1 selects RSL register 1 and
so on. VRSL3-0 is latched on the rising
edge of CLK (see the vertical round,
select, and limit sections for a com-
plete discussion).
LINE BUFFER
LINE BUFFER
LINE BUFFER
FIGURE 5. DIMENSIONALLY SEPARATE MODE: V TO H
DIN11-0
12
LINE BUFFER
LINE BUFFER
OE — Output Enable
When OE is LOW, DOUT11-0 is
enabled for output. When OE is
HIGH, DOUT11-0 is placed in a
high-impedance state.
LINE BUFFER
12
HORIZONTAL FILTER
LINE BUFFER
LINE BUFFER
LINE BUFFER
12
HPAUSE — LF InterfaceTM Pause
LINE BUFFER
DOUT11-0
When HPAUSE is HIGH, the Hori-
zontal LF InterfaceTM loading
sequence is halted until HPAUSE is
returned to a LOW state. This
effectively allows the user to load
coefficients and Control Registers at a
slower rate than the master clock (see
the LF InterfaceTM section for a full
discussion).
VPAUSE — LF InterfaceTM Pause
When VPAUSE is HIGH, the Vertical
LF InterfaceTM loading sequence is
halted until VPAUSE is returned to a
LOW state. This effectively allows the
user to load coefficients and Control
Registers at a slower rate than the
master clock (see the LF InterfaceTM
section for a full discussion).
OPERATIONAL MODES
Dimensionally Separate
In Dimensionally Separate Mode, the
horizontal and vertical filters are
cascaded together to form a
two-dimensional image filter (see
Figures 4 and 5). Bit 1 in Configura-
tion Register 4 determines the cascade
order. If this bit is set to “0”, data on
DIN11-0 is fed into the horizontal filter
first. The horizontal filter then feeds
data into the vertical filter. If this bit
is set to “1”, data on DIN11-0 is fed
into the vertical filter first. The
vertical filter then feeds data into the
horizontal filter.
Orthogonal
In Orthogonal Mode, the horizontal
and vertical filters are used concur-
rently to implement an orthogonal
kernel on the input data (see Figure 6).
Video Imaging Products
5 11/08/2001-LDS.3310-H

5 Page





LF3310 arduino
DEVICES INCORPORATED
LF3310
Horizontal / Vertical Digital Image Filter
TABLE 8. HCF/VCF11-9 DECODE
11 10 9 DESCRIPTION
0 0 0 Coefficient Banks
0 0 1 Configuration Registers
0 1 0 Horizontal Select Registers
0 1 1 Vertical Select Registers
1 0 0 Horizontal Round Registers
1 0 1 Vertical Round Registers
1 1 0 Horizontal Limit Registers
1 1 1 Vertical Limit Registers
Vertical Rounding
The vertical filter output may be
rounded by adding the contents of
one of the sixteen vertical round
registers to the vertical filter output
(see Figure 11). Each round register is
32-bits wide and user-programmable.
This allows the filter’s output to be
rounded to any precision required.
Since any 32-bit value may be
programmed into the round registers,
the device can support complex
rounding algorithms as well as
standard Half-LSB rounding.
VRSL3-0 determines which of the
sixteen vertical round registers are
used in the rounding operation. A
value of 0 on VRSL3-0 selects vertical
round register 0. A value of 1 selects
vertical round register 1 and so on.
VRSL3-0 may be changed every clock
cycle if desired. This allows the
rounding algorithm to be changed
every clock cycle. This is useful when
filtering interleaved data. If rounding
is not desired, a round register should
be loaded with 0 and selected as the
register used for rounding. Round
register loading is discussed in the LF
InterfaceTM section.
Vertical Select
The word width of the vertical filter
output is 32-bits. However, only
12-bits may be sent to the filter
output. The vertical filter select
circuitry determines which 12-bits are
passed (see Table 1). The vertical
select registers control the vertical
select circuitry. There are sixteen
vertical select registers. Each select
TABLE 9. HRZ. ROUND REGISTERS
REGISTER
ADDRESS (HEX)
0 800
1 801
14 80E
15 80F
TABLE 10. HRZ. SELECT REGISTERS
REGISTER
ADDRESS (HEX)
0 400
1 401
14 40E
15 40F
TABLE 11. HRZ. LIMIT REGISTERS
REGISTER
ADDRESS (HEX)
0 C00
1 C01
14 C0E
15 C0F
register is 5-bits wide and
user-programmable. VRSL3-0 deter-
mines which of the sixteen vertical
select registers are used in the vertical
select circuitry. A value of 0 on
VRSL3-0 selects vertical select register
0. A value of 1 selects vertical select
register 1 and so on. VRSL3-0 may be
changed every clock cycle if desired.
This allows the 12-bit window to be
changed every clock cycle. This is
useful when filtering interleaved
data. Select register loading is
discussed in the LF InterfaceTM
section.
Vertical Limiting
An output limiting function is pro-
vided for the output of the vertical
filter. The vertical limit registers
determine the valid range of output
values when limiting is enabled (Bit 0
in Configuration Register 5). There
TABLE 12. VRT. ROUND REGISTERS
REGISTER
ADDRESS (HEX)
0 A00
1 A01
14 A0E
15 A0F
TABLE 13. VRT. SELECT REGISTERS
REGISTER
ADDRESS (HEX)
0 600
1 601
14 60E
15 60F
TABLE 14. VRT. LIMIT REGISTERS
REGISTER
ADDRESS (HEX)
0 E00
1 E01
14 E0E
15 E0F
are sixteen 24-bit vertical limit
registers. VRSL3-0 determines which
vertical limit register is used during
the limit operation. A value of 0 on
VRSL3-0 selects vertical limit register
0. A value of 1 selects vertical limit
register 1 and so on. Each limit
register contains both an upper and
lower limit value. If the value fed to
the limiting circuitry is less than the
lower limit, the lower limit value is
passed as the filter output. If the
value fed to the limiting circuitry is
greater than the upper limit, the upper
limit value is passed as the filter output.
VRSL3-0 may be changed every clock
cycle if desired. This allows the limit
range to be changed every clock cycle.
This is useful when filtering interleaved
data. When loading limit values into
the device, the upper limit must be
greater than the lower limit. Limit
register loading is discussed in the LF
InterfaceTM section.
Video Imaging Products
11 11/08/2001-LDS.3310-H

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