DataSheet.es    


PDF TC55NEM216AFTN55 Data sheet ( Hoja de datos )

Número de pieza TC55NEM216AFTN55
Descripción (TC55NEM216AFTN55 / TC55NEM216AFTN77) MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Fabricantes Toshiba Semiconductor 
Logotipo Toshiba Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de TC55NEM216AFTN55 (archivo pdf) en la parte inferior de esta página.


Total 11 Páginas

No Preview Available ! TC55NEM216AFTN55 Hoja de datos, Descripción, Manual

TC55NEM216AFTN55,70
www.DaTtaESNheTeAt4TUI.cVoEm TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55NEM216AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by
16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V ±
10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1 µA standby
current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device
and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB ,
UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of 40° to 85°C, the TC55NEM216AFTN can be used in environments exhibiting extreme
temperature conditions. The TC55NEM216AFTN is available in a plastic 54-pin thin-small-outline package
(TSOP).
FEATURES
Low-power dissipation
Operating: 15 mW/MHz (typical)
Single power supply voltage of 5 V ± 10%
Power down features using CE
Data retention supply voltage of 2.0 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of 40° to 85°C
Standby Current (maximum): 20 µA
Access Times (maximum):
TC55NEM216AFTN
55 70
Access Time
55 ns
70 ns
CE Access Time
55 ns
70 ns
OE Access Time
30 ns
35 ns
Package:
TSOP II54-P-400-0.80
(Weight: g typ)
PIN ASSIGNMENT (TOP VIEW)
54 PIN TSOP
NC
A3
A2
A1
A0
I/O16
I/O15
VDD
GND
I/O14
I/O13
UB
CE
OP
R/W
I/O12
I/O11
GND
VDD
I/O10
I/O9
NC
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 A4
53 A5
52 A6
51 A7
50 NC
49 I/O1
48 I/O2
47 VDD
46 GND
45 I/O3
44 I/O4
43 LB
42 OE
41 OP
40 NC
39 I/O5
38 I/O6
37 GND
36 VDD
35 I/O7
34 I/O8
33 A8
32 A9
31 A10
30 A11
29 A12
28 NC
PIN NAMES
A0~A17 Address Inputs
CE Chip Enable
R/W Read/Write Control
OE Output Enable
LB , UB Data Byte Control
I/O1~I/O16 Data Inputs/Outputs
VDD
GND
Power (+5 V)
Ground
NC No Connection
OP* Option
*: OP pin must be open or connected to GND.
2002-07-04 1/11

1 page




TC55NEM216AFTN55 pdf
TC55NEM216AFTN55,70
www.DaAtaCSheCetH4UA.cRomACTERISTICS AND OPERATING CONDITIONS
(Ta = −40° to 85°C, VDD = 5 V ± 10%)
READ CYCLE
SYMBOL
PARAMETER
tRC
tACC
tCO
tOE
tBA
tCOE
tOEE
tBE
tOD
tODO
tBD
tOH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
TC55NEM216AFTN
55 70
MIN MAX MIN MAX
55 70
55 70
55 70
30 35
55 70
55
00
55
25 30
25 30
25 30
10 10
UNIT
ns
WRITE CYCLE
TC55NEM216AFTN
SYMBOL
PARAMETER
55 70 UNIT
MIN MAX MIN MAX
tWC Write Cycle Time
55 70
tWP Write Pulse Width
40 50
tCW Chip Enable to End of Write
45 55
tBW Data Byte Control to End of Write
45 55
tAS Address Setup Time
tWR Write Recovery Time
00
ns
00
tODW
R/W Low to Output High-Z
25 30
tOEW
R/W High to Output Active
00
tDS Data Setup Time
25 30
tDH Data Hold Time
00
Note: tOD, tODO, tBD and tODW are specified in time when an output becomes high impedance, and are not judged depending on
an output voltage level.
AC TEST CONDITIONS
PARAMETER
Input pulse level
tR, tF
Timing measurements
Reference level
Output load
TEST CONDITION
0.4 V, 2.4 V
5 ns
1.5 V
1.5 V
100 pF + 1 TTL Gate
2002-07-04 5/11

5 Page





TC55NEM216AFTN55 arduino
www.DataSheet4U.com
TC55NEM216AFTN55,70
RESTRICTIONS ON PRODUCT USE
000707EBA
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the Handling Guide for Semiconductor Devices,or TOSHIBA Semiconductor Reliability
Handbooketc..
The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (Unintended Usage). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customers own risk.
The products described in this document are subject to the foreign exchange and foreign trade laws.
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
The information contained herein is subject to change without notice.
2002-07-04 11/11

11 Page







PáginasTotal 11 Páginas
PDF Descargar[ Datasheet TC55NEM216AFTN55.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
TC55NEM216AFTN55(TC55NEM216AFTN55 / TC55NEM216AFTN77) MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOSToshiba Semiconductor
Toshiba Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar