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PDF NCP5395 Data sheet ( Hoja de datos )
| Número de pieza | NCP5395 | |
| Descripción | CPU Applications | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP5395www.DataSheet4U.com
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2/3/4-Phase Controller with
On Board Gate Drivers for
CPU Applications
The NCP5395 provides up to a four−phase buck solution which
combines differential voltage sensing, differential phase current
sensing, adaptive voltage positioning, and on board gate drivers.
Dual−edge pulse−width modulation (PWM) combined with inductor
current sensing reduces system cost by providing the fastest initial
response to dynamic load events. Dual−edge multiphase modulation
reduces the total bulk and ceramic output capacitance required to meet
transient regulation specifications.
The on board gate drivers includes adaptive non overlap and power
saving operation. A high performance operational error amplifier is
provided to simplify compensation of the system. Patented Dynamic
Reference Injection further simplifies loop compensation by
eliminating the need to compromise between closed−loop transient
response and Dynamic VID performance.
Features
• Meets Intel’s VR11.1 Specifications
• Meets AMD 6 Bit Code Specifications
• Dual−edge PWM for Fastest Initial Response to Transient Loading
• High Performance Operational Error Amplifier
• Internal Soft Start
• Dynamic Reference Injection (Patent #US07057381)
• DAC Range from 0.5 V to 1.6 V
• DAC Feed Forward Function (Patient Pending)
• ±0.5% DAC Voltage Accuracy from 1.0 V to 1.6 V
• True Differential Remote Voltage Sensing Amplifier
• Phase−to−Phase Current Balancing
• “Lossless” Differential Inductor Current Sensing
• Differential Current Sense Amplifiers for Each Phase
• Adaptive Voltage Positioning (AVP)
• Oscillator Frequency Range of 125 kHz − 1 MHz
• Latched Over Voltage Protection (OVP)
• Guaranteed Startup into Pre−Charged Loads
• Threshold Sensitive Enable Pin for VTT Sensing
• Power Good Output with Internal Delays
• Thermally Compensated Current Monitoring
• Thermal Shutdown Protection
• Adaptive−Non−Overlap Gate Drive Circuit
• Output Disable Control Turn Off of Both Phase Pair MOSFETs
• This is a Pb−Free Device
Applications
• Desktop Processors
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
http://onsemi.com
1 48
QFN48
CASE 485K
PLASTIC
MARKING DIAGRAM
48
1
NCP5395
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
48
1
VBPIGDS03I
VVIIDD21
VVVIIIDDD543
VID6
VID7/AMD
ROILSIMC
AGND
Down−bonded to
Exposed Flag
BG1
G4
CCEVNRSSR11PNDY
CCCCSSSS3322PNPN
CCSS44PN
ORDERING INFORMATION
Device
Package
Shipping†
NCP5395MNR2G QFN48 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2008
July, 2008 − Rev. P5
1
Publication Order Number:
NCP5395/D
1 page  
www.DataSheet4U.com
NCP5395
VTT
PSI#_CPU
VVVVVIIIIIDDDDD02431
VVVIIIDDD765
RLIM10
IMON
12V_FILTER
2 1 12V_FILTER
D
G
S
DD
GG
SS
PWM3_SENSE_N
PWM3_SENSE_P
VCCP
RFB11CFB6
13
14
IMON
VSP
VBST3 48
TG3 47
RF5
CF5
15 VSN
RFB9 16 DIFFOUT
SWN3 46
DRVON 45 DRVON
17 COMP
CH5
18
RDRP1119
VFB
VDRP
NCP5395
48L 7x7 QFN
FLAG = GND
BST2 44
TG2 43
SWN2 42
CDFB5
RDFB5
20 VDFB
21 CSSUM
BG2
41
12V_FILTER
VCCP 40
RT12
RISO11 RISO12
22 DAC
23 GND
SWN1 39
TG1 38
+5.0V
24 VCC
BST1 37
21
12V_FILTER
D
G
S
DD
G G PWM2_SENSE_N
S S PWM2_SENSE_P
21
12V_FILTER
D
G
S
VCCP
D D PWM1_SENSE_N
VTT
PWM4_GATE
PWM1_SENSE_P
G
S
G
S
PWM1_SENSE_P
ENABLE
PWM1_SENSE_N
12V_FILTER
PWM2_SENSE_P
2
1
PWM2_SENSE_N
PWM3_SENSE_P
PWM3_SENSE_N
DRVON
PWM4_GATE
PWM4_SENSE_P
VCC BST
OD
IN
4
3
2
1
8
7
5
6
DRH
SW
DRL
PGND
NCP5359
PWM4_SENSE_N
12V_FILTER
D
G
S
DD
GG
SS
PWM4_SENSE_N
PWM4_SENSE_P
Figure 4. Typical 4 Phase Application
http://onsemi.com
5
5 Page 
NCP5395
www.DataESLheEeCt4TUR.cIComAL CHARACTERISTICS
0°C < TA < 70°C; 0°C < TJ < 125°C; 4.75 < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF unless otherwise noted.
Parameter
Test Conditions
Min Typ Max Unit
VR_RDY (Power Good) OUTPUT
VR_RDY Rise Time
VR_RDY Output Voltage at Power−up
VR_RDY High − Output Leakage Current
External pull−up of 1 KW to 1.25 V,
CTOT = 45 pF, DVo = 10% to 90%
VR_RDY pulled up to 5 V via 2 kW,
tR(VCC) ≤ 3 x tR(5V)
100 ms ≤ tR(VCC) ≤ 20 ms
VR_RDY = 5.5 V via 1 K
−
−
−
100 150
− 1.0
ns
V
− 0.1 mA
VR_RDY Upper Threshold Voltage (INTEL)
VCore Increasing, DAC = 1.3 V
− 300 250 mV
(below
DAC)
VR_RDY Lower Threshold Voltage (INTEL)
VCore Decreasing, DAC = 1.3 V
390 350 300 mV
(below
DAC)
VR_RDY Lower Threshold Voltage (AMD)
VCore Increasing, DAC = 1.3 V
−
TBD
TBD
mV
(below
DAC)
VR_RDY Lower Threshold Voltage (AMD)
VCore Decreasing, DAC = 1.3 V
TBD
TBD
TBD
mV
(below
DAC)
VR_RDY Rising Delay
VCore Increasing
− TBD −
ms
VR_RDY Falling Delay
VCore Decreasing
− 5.0 − ms
PWM G4 OUTPUT
Output High Voltage
Mid Output Voltage
Sourcing 500 mA
3.0 −
−
1.4 1.5 1.6
V
Output Low Voltage
Sinking 500 mA
− − 0.7 V
Delay + Rise Time
Delay + Fall Time
Tri−State Output Leakage
CL (PCB) = 50 pF,
DVo = VCC to GND
CL (PCB) = 50 pF,
DVo = GND to VCC
Gx = 2.5 V, x = 1−4
− 10 15 ns
− 10 15 ns
− − 1.5 mA
Output Impedance −
HI or LO State
Max Resistance to VCC (HI) or
GND (LO)
− 75 150 W
Minimum VCC for Valid PWM Output Level
PWM 4 2/3/4 Phase Detection
− − 2.0 V
2 Phase Mode
4 Phase Mode
Note Gate 4 tied to VCC
Note Gate Driver will pull to 1.5 V
3.2
1.2
− VCC V
− 2.8 V
3 Phase Mode
Note Gate 4 tied to GND
0 − 0.8 V
DIGITAL SOFT−START
Soft−Start Ramp Time
DAC = 0 to DAC = 1.1 V
1.0 − 1.3 ms
VR11 Vboot time
VID7/VR11/AMD/LEGACY INPUT
Not used in Legacy Startup
400 500 600
ms
VID Threshold
450 600 770 mV
VR11 Input Bias Current
−100
−
100 nA
3. Design guaranteed.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
5. Guaranteed by design; not tested in production.
6. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
7. No DAC offset is implemented for AMD operation.
http://onsemi.com
11
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet NCP5395.PDF ] | |
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