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PDF DS34S101 Data sheet ( Hoja de datos )

Número de pieza DS34S101
Descripción (DS34S101 - DS34S108) Single/Dual/Quad/Octal TDM-over-Packet Chip
Fabricantes Maxim Integrated Products 
Logotipo Maxim Integrated Products Logotipo



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No Preview Available ! DS34S101 Hoja de datos, Descripción, Manual

Rev: 101708
www.DataSheet4U.com
ABRIDGED DATA SHEET
DS34S101, DS34S102, DS34S104, DS34S108
Single/Dual/Quad/Octal TDM-over-Packet Chip
General Description
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
compliant devices allow up to eight E1, T1 or serial
streams or one high-speed E3, T3, STS-1 or serial
stream to be transported transparently over IP, MPLS
or Ethernet networks. Jitter and wander of recovered
clocks conform to G.823/G.824, G.8261, and TDM
specifications. TDM data is transported in up to 64
individually configurable bundles. All standards-
based TDM-over-packet mapping methods are
supported except AAL2. Frame-based serial HDLC
data flows are also supported. The high level of
integration available with the DS34S10x devices
minimizes cost, board space, and time to market.
Applications
TDM Circuit Extension Over PSN
o Leased-Line Services Over PSN
o TDM Over GPON/EPON
o TDM Over Cable
o TDM Over Wireless
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC-Based Traffic Transport Over PSN
Features
Transport of E1, T1, E3, T3 or STS-1 TDM or
CBR Serial Signals Over Packet Networks
Full Support for These Mapping Methods:
SAToP, CESoPSN, TDMoIP (AAL1), HDLC,
Unstructured, Structured, Structured with CAS
Adaptive Clock Recovery, Common Clock,
External Clock and Loopback Timing Modes
On-Chip TDM Clock Recovery Machines, One
Per Port, Independently Configurable
Clock Recovery Algorithm Handles Network
PDV, Packet Loss, Constant Delay Changes,
Frequency Changes and Other Impairments
64 Independent Bundles/Connections
Multiprotocol Encapsulation Supports IPv4,
IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet
VLAN Support According to 802.1p and 802.1Q
10/100 Ethernet MAC Supports MII/RMII/SSMII
Selectable 32-Bit, 16-Bit or SPI Processor Bus
Operates from Only Two Clock Signals, One for
Clock Recovery and One for Packet Processing
Glueless SDRAM Buffer Management
Low-Power 1.8V Core, 3.3V I/O
See detailed feature list in Section 5 .
TDM
Interfaces
Functional Diagram
CPU
Bus
DS34S108
Circuit
Emulation
Engine
10/100
Ethernet
MAC
xMII
Interface
Buffer
Manager
Clock
Adapters
SDRAM
Interface
Clock Inputs
Ordering Information
PART
PORTS TEMP RANGE PIN-PACKAGE
DS34S101GN*
1 -40°C to +85°C 256 TECSBGA
DS34S101GN+* 1 -40°C to +85°C 256 TECSBGA
DS34S102GN* 2 -40°C to +85°C 256 TECSBGA
DS34S102GN+* 2 -40°C to +85°C 256 TECSBGA
DS34S104GN
4 -40°C to +85°C 256 TECSBGA
DS34S104GN+
4 -40°C to +85°C 256 TECSBGA
DS34S108GN
8 -40°C to +85°C 484 HSBGA
DS34S108GN+ 8 -40°C to +85°C 484 HSBGA
+Denotes lead-free/RoHS-compliant package (explanation).
*Future product—contact factory for availability.
________________________________________________________ Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering
information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

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DS34S101 pdf
ABRIDGED DATA SHEET
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
www.DataSheet4U.com
Figure 3-2. TDMoP in Cellular Backhaul
Other Possible Applications
Point-to-Multipoint TDM Connectivity over IP/Ethernet
The DS34S10x devices support NxDS0 TDMoP connections (known as bundles) with or without CAS (Channel
Associated Signaling). There is no need for an external TDM cross-connect, since the packet domain can be used
as a virtual cross-connect. Any bundle of timeslots can be directed to another remote location on the packet
domain.
HDLC Transport over IP/MPLS
TDM traffic streams often contain HDLC-based control channels and data traffic. These data streams, when
transported over a packet domain, should be treated differently than the time-sensitive TDM payload. DS34S10x
devices can terminate HDLC channels in the TDM streams and optionally map them into IP/MPLS/Ethernet for
transport. All HDLC-based control protocols (ISDN BRI and PRI, SS7 etc.) and all HDLC data traffic can be
managed and transported.
Using a Packet Backplane for Multiservice Concentrators
A communications device with all the above-mentioned capabilities can use a packet-based backplane instead of
the more expensive TDM bus option. This enables a cost-effective and future-proof design of communication
platforms with full support for both legacy and next-generation services.
Rev: 101708
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DS34S101 arduino
ABRIDGED DATA SHEET
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
www.DataSheet4U.com
PIN NAME
TYPE PIN DESCRIPTION
H_WR_BE2_N / SPI_SEL_N
I Host Write Enable Byte 2 or SPI Chip Select (Active Low)
H_WR_BE3_N / SPI_CI
I Host Write Enable Byte 3 (Active Low) or SPI Clock Invert
H_READY_N
Oz Host Ready Output (Active Low)
H_INT
O Host Interrupt Output.
JTAG Interface
JTRST_N
JTCLK
JTMS
JTDI
JTDO
Ipu JTAG Test Reset
Ipd JTAG Test Clock
Ipu JTAG Test Mode Select
Ipu JTAG Test Data Input
Oz JTAG Test Data Output
Reset and Factory Test Pins
RST_SYS_N
Ipu
HIZ_N
I
SCEN
Ipd
STMD
Ipd
MBIST_EN
I
MBIST_DONE
O
MBIST_FAIL
O
TEST_CLK
O
TST_CLD
I
System Reset (Active Low)
High Impedance Enable (Active Low)
Used for factory tests.
Used for factory tests.
Used for factory tests.
Used for factory tests.
Used for factory tests
Used for factory tests.
Used for factory tests. DS34S104 only.
Power and Ground
DVDDC
DVDDIO
DVSS
ACVDD1, ACVDD2
ACVSS1, ACVSS2
P 1.8V Core Voltage for TDM-over-Packet Digital logic (17 pins)
P 3.3V for I/O Pins (16 pins)
P Ground for TDM-over-Packet logic and I/O Pins (31 pins)
P 1.8V for CLAD Analog Circuits
P Ground for CLAD Analog Circuits
Note 1: In pin names, the suffix “n” stands for port number: n=1 to 8 for DS34S108; n=1 to 4 for DS34S104; n=2 for DS34S102; n=1 for
DS34S101. All pin names ending in “_N” are active low.
Note 2:
All pins, except power and analog pins, are CMOS/TTL unless otherwise specified in the pin description.
PIN TYPES
I = input pin
IPD = input pin with internal 50kΩ pulldown to DVSS
IPU = input pin with internal 50kΩ pullup to DVDDIO
IO = input/output pin
IOPD = input/output pin with internal 50kΩ pulldown to DVSS
IOPU = input/output pin with internal 50kΩ pullup to DVDDIO
O = output pin
OZ = output pin that can be placed in a high-impedance state
P = power-supply or ground pin
Rev: 101708
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