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PDF LF2301JC25 Data sheet ( Hoja de datos )

Número de pieza LF2301JC25
Descripción Image Resampling Sequencer
Fabricantes LOGIC Devices Incorporated 
Logotipo LOGIC Devices Incorporated Logotipo



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No Preview Available ! LF2301JC25 Hoja de datos, Descripción, Manual

DEVICES INCORPORATED
DEVICES INCORPORATED
LF2301
Image ResampliLngFS2eq3u0en1cer
Image Resampling Sequencer
FEATURES
DESCRIPTION
u 40 MHz Clock Rate
u High-Speed Image Manipulation
u Maximum Image Size: 4096 x 4096
Pixels
u Supports Following Interpolation
Algorithms:
• Nearest-Neighbor
• Bilinear Interpolation
• Cubic Convolution
u Applications:
• Video Special-Effects
• Image Recognition
• High-Speed Data Encoding/
Decoding
u Replaces TRW/Raytheon/Fairchild
TMC2301
u 68-pin PLCC, J-Lead
The LF2301 is a self-sequencing
address generator designed to filter
a two-dimensional image or remap
and resample it from one set of
Cartesian coordinates (x,y) into a
new set (u,v).
The LF2301 can resample digitized
images or perform such manipula-
tions as rotation, panning, zooming,
and warping as well as compression
in real-time.
By using two LF2301s in a Image
Transformation System (ITS),
nearest-neighbor, bilinear interpola-
tion, and cubic convolution algo-
rithms, with kernel sizes up to 4 x 4
pixels, are all possible (see Figure 1).
This system can also implement
simple static filters with kernel sizes
up to 16 x 16 pixels.
DETAILS OF OPERATION
Most video applications use a pair
of LF2301s in tandem to construct
an ITS. One LF2301 is the row
coordinate generator (x to u) and the
other is the column generator (y to
v). External RAM is needed for
storage of the interpolation coeffi-
cient lookup table, as well as for
buffers of the source and destination
images. An external Multiplier-
Accumulator is required when
performing interpolation or imple-
menting static filters.
The ITS is capable of performing the
general second-order coordinate
transformation of the form:
x(u,v) = Au2+Bu+Cuv+Dv2+Ev+F
y(u,v) = Gu2+Hu+Kuv+Lv2+Mv+N
LF2301 BLOCK DIAGRAM
LDR WEN
B3-0 P11-0
PARAMETER
STORAGE
NOOP
INTER
INIT
CONTROL
WALK COUNT
where parameters A through N of
the transform are user-defined.
The system steps sequentially
through each pixel in the “target”
image lying within a user-defined
ACC
DONE
rectangle. For each “target” pixel
END at (u,v), the LF2301 points to a
corresponding “source” pixel at
(x,y).
SOURCE
ADDRESS
GENERATOR
FRACTION
INTEGER
INPUT IMAGE
BOUNDARY
COMPARATOR
TARGET
ADDRESS
GENERATOR
CA7-0
X11-0
CZERO
UWRI
U11-0
OETA
Video Imaging Products
2-1 08/16/2000–LDS.2301-H

1 page




LF2301JC25 pdf
DEVICES INCORPORATED
LF2301
Image Resampling Sequencer
addresses. An example of an ITS
implemented with two LF2301s is
shown in Figure 1. In this system the
following components are used: two
LF2301s, a multiplier-accumulator
(MAC), interpolation coefficient RAM,
and source/target image RAM.
Maximum image size is 4096 x 4096
pixels. Data word size is determined
by the word size of the external RAM.
A typical ITS performs image transfor-
mations as follows:
a. The LF2301s generate sequential
pixel addresses (left to right, top to
bottom) which fill the rectangle in the
target image RAM defined by
(UMIN,VMIN) and (UMAX +1, VMAX).
It is important to note that the U value
of the last pixel address on each line of
the target RAM is UMAX + 1.
b. The LF2301s calculate the address
of the corresponding pixel in the
source image RAM for each target
pixel address generated.
c. If interpolation is needed, the
external MAC sums the products of
the source pixels and the interpola-
tion coefficients. Control signals for
the MAC and address signals for the
interpolation coefficient RAM are
provided by the LF2301s.
d. The new pixel value is written into
the target image RAM.
The LF2301s generate source pixel
addresses according to the following
general second order equations:
x = Au2 + Bu + Cuv + Dv2 + Ev + F
y = Gu2 + Hu + Kuv + Lv2 + Mv + N
where (x,y) and (u,v) are the source
and target coordinates respectively.
A through N are user-defined param-
eters. The actual second order equa-
tions used are shown in Figure 3.
FIGURE 2. TEST MODE DATA ROUTING
28-BIT INTERNAL
ACCUMULATOR
1
SIGN
12
12
4 12
7
WALK COUNTER
4
4
X11-0/T11-0
CA7-4
CA3-0
FIGURE 3. ADDRESS TRANSFORMATION EQUATIONS
x = x0 +
dx m +
du
dx
dv
n+
d2x
dudv
mn +
d2x
du2
m2– m
2
+
d2x
dv2
n2– n
2
+ FOV · CAX(w) + FOV · m · CAX(ker)
y = y0 +
dy m +
du
dy
dv
n+
d2y
dudv
mn +
d2y
du2
m2– m
2
+
d2y
dv2
n2– n
2
+ FOV · CAY(w) + FOV · m · CAY(ker)
u = UMIN + m
v = VMIN + n
NOTE: m2– m APPROXIMATES THE EXPONENTIAL CHARACTERISTIC OF m2.
2
Video Imaging Products
2-5 08/16/2000–LDS.2301-H

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LF2301JC25 arduino
DEVICES INCORPORATED
LF2301
Image Resampling Sequencer
Pass 1 of Two-Pass Operation
Pass 1 of the two-pass operation
performs horizontal filtering on an
image as shown in Figure 9. This
mode is selected by loading M1-0 with
“01.” In this example, a horizontal
filter with a kernel size of 3 pixels is
desired. Loading K3-0 with “0010”
selects a kernel size of 3. The first
pixel selected is determined by x0 and
y0. In this example, the first pixel is
(0,0). In this case, the LF2301s should
address consecutive pixels during each
pixel walk. For this to occur, FOV must
be set to 1 (F2-0 loaded with “001”).
After the last pixel of a pixel walk has
been selected, the next pixel address is
determined by adding dx/du to the
current X address and by adding dy/
du to the current Y address (unless the
kernel just completed was the last for
that line). At the end of the first pixel
walk, pixel (2,0) is addressed. Since
the first pixel of the next pixel walk
should be (1,0), dx/du is selected to be
-1 and dy/du is selected to be 0. After
the last pixel of the last pixel walk on
the first line has been selected, the first
FIGURE 9. PASS 1 OF TWO-PASS
01234
-1
123
0
456
1
7
2
3
1 = 1st pixel of 1st walk,
2 = 1st pixel of 2nd walk, etc.
pixel address of the second line is
determined by adding dx/dv to x0
and by adding dy/dv to y0. Since the
first pixel of the first pixel walk on the
second line should be (0,1), dx/dv is
selected to be 0 and dy/dv is selected
to be 1. Second order differential
terms are not used in this filter and are
therefore set to 0.
TABLE 9. PARAMETER REGISTERS
ADDR Row (HEX) Column (HEX)
0000
0001
000
FFF
000
FFF
0010
0011
000
040
000
140
0100
0101
000
1FF
000
000
0110
0111
000
200
000
201
1000
1001
000
000
000
000
1010
1011
000
000
000
000
1100
1101
000
000
000
000
1110
1111
005
006
005
006
UMIN and VMIN are both selected to
be 5. UMAX and VMAX are both
selected to be 6. Table 9 shows the
values loaded into all Parameter
Registers. Table 10 shows the ITS
outputs for the Pass 1 of a Two-Pass
operation.
TABLE 10. ITS OUTPUTS FOR PASS 1 OF TWO-PASS
Cycle x y CAx (HEX) CAy (HEX) u
1 0 0 00
00 x
2 0 0 00
00 x
3 0 0 00
00 x
4 0 0 00
5 1 0 01
6 2 0 02
00 x
01 x
02 x
7 1 0 00
8 2 0 01
9 3 0 02
00 5
01 5
02 5
10 2 0
11 3 0
12 4 0
00
01
02
00 6
01 6
02 6
13 0 1
14 1 1
15 2 1
00
01
02
00 7
01 7
02 7
16 1 1
17 2 1
18 3 1
00
01
02
00 5
01 5
02 5
19 2 1
20 3 1
21 4 1
00
01
02
00 6
01 6
02 6
22 0 0
23 1 0
24 2 0
00
01
02
00 7
01 7
02 7
v INIT ACC UWRI ENDx ENDy DONE
x101000
x001000
x001000
x001000
x010100
x011100
5001100
5010000
5011000
5001000
5010010
5011010
5001010
5010110
5011110
6001110
6010010
6011010
6001010
6010001
6011001
6001001
6010101
6011101
Video Imaging Products
2-11
08/16/2000–LDS.2301-H

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