|
|
PDF LF2246QC15 Data sheet ( Hoja de datos )
| Número de pieza | LF2246QC15 | |
| Descripción | 11 x 10-bit Image Filter | |
| Fabricantes | LOGIC Devices Incorporated | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LF2246QC15 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
|
No Preview Available !
DEVICES INCORPORATED
DEVICES INCORPORATED
LF2246
11 x 10-bLit FIm2ag2e4Fi6lter
11 x 10-bit Image Filter
FEATURES
DESCRIPTION
u 66 MHz Data and Coefficient Input
and Computation Rate
u Four 11 x 10-bit Multipliers with
Individual Data and Coefficient
Inputs and a 25-bit Accumulator
u User-Selectable Fractional or
Integer Two’s Complement Data
Formats
u Fully Registered, Pipelined Archi-
tecture
u Input and Output Data Registers,
with User-Configurable Enables
u Three-State Outputs
u Fully TTL Compatible
u Ideally Suited for Image Processing
and Filtering Applications
u Replaces TRW/Raytheon/Fairchild
TMC2246
u 120-pin PQFPP
The LF2246 consists of an array of
four 11 x 10-bit registered multipliers
followed by a summer and a 25-bit
accumulator. All multiplier inputs
are user accessible and can be up-
dated every clock cycle with either
fractional or integer two’s comple-
ment data. The pipelined architecture
has fully registered input and output
ports and an asynchronous three-state
output enable control to simplify the
design of complex systems. The
pipeline latency for all inputs is five
clock cycles.
Storage for mixing and filtering
coefficients can be accomplished by
holding the data or coefficient inputs
over multiple clock cycles. A 25-bit
accumulator path allows cumulative
word growth which may be internally
rounded to 16 bits. Output data is
updated every clock cycle and may be
held under user control. All inputs,
outputs, and controls are registered
on the rising edge of clock, except for
OEN. The LF2246 operates at a clock
rate of 66 MHz over the full tempera-
ture and supply voltage ranges.
The LF2246 is applicable for perform-
ing pixel interpolation in image
manipulation and filtering applica-
tions. The LF2246 can perform a
bilinear interpolation of an image (4-
pixel kernels) at real-time video rates
when used with an image resampling
sequencer. Larger kernels or more
complex functions can be realized by
utilizing multiple devices.
Unrestricted access to all data and
coefficient input ports provides the
LF2246 with considerable flexibility in
applications such as digital filters,
adaptive FIR filters, mixers, and other
similar systems requiring high-speed
processing.
LF2246 BLOCK DIAGRAM
D19–0
ENSEL
C110–0
ENB1
D29–0
C210–0
ENB2
D39–0
C310–0 ENB3
D49–0
C410–0
ENB4
10 11 10 11
10 11 10 11
22
ACC
22
25
FSEL
OEN
CLK
MS LS
TO ALL REGISTERS
S15–0
2-11
OCEN
Video Imaging Products
08/16/2000–LDS.2246-K
1 page  
DEVICES INCORPORATED
LF2246
11 x 10-bit Image Filter
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated by:
where
NCV2 F
4
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 30 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
CL
IOL
VTH
IOH
FIGURE B. THRESHOLD LEVELS
tENA
tDIS
OE 1.5 V
1.5 V
Z0
1.5 V
VOL* 0.2 V
3.5V Vth
0Z
Z1
1.5 V
VOH* 0.2 V
1Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
Video Imaging Products
2-15
08/16/2000–LDS.2246-K
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet LF2246QC15.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LF2246QC15 | 11 x 10-bit Image Filter | LOGIC Devices Incorporated |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |