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PDF MAX11613 Data sheet ( Hoja de datos )

Número de pieza MAX11613
Descripción (MAX11612 - MAX11617) 4-/8-/12-Channel ADCs
Fabricantes Maxim Integrated Products 
Logotipo Maxim Integrated Products Logotipo



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No Preview Available ! MAX11613 Hoja de datos, Descripción, Manual

19-4561; Rev 0; 4/09
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel, 2-Wire Serial, 12-Bit ADCs
General Description
The MAX11612–MAX11617 low-power, 12-bit, multi-
channel analog-to-digital converters (ADCs) feature
internal track/hold (T/H), voltage reference, clock, and an
I2C-compatible 2-wire serial interface. These devices
operate from a single supply of 2.7V to 3.6V
(MAX11613/MAX11615/MAX11617) or 4.5V to 5.5V
(MAX11612/MAX11614/MAX11616) and require only
670µA at the maximum sampling rate of 94.4ksps.
Supply current falls below 230µA for sampling rates
under 46ksps. AutoShutdown™ powers down the
devices between conversions, reducing supply current
to less than 1µA at low throughput rates. The
MAX11612/MAX11613 have 4 analog input channels
each, the MAX11614/MAX11615 have 8 analog input
channels each, while the MAX11616/MAX11617 have
12 analog input channels each. The fully differential
analog inputs are software configurable for unipolar or
bipolar, and single-ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX11613/
MAX11615/MAX11617 feature a 2.048V internal refer-
ence and the MAX11612/MAX11614/MAX11616 feature
a 4.096V internal reference.
The MAX11612/MAX11613 are available in an 8-pin
µMAX® package. The MAX11614–MAX11617 are avail-
able in a 16-pin QSOP package. The MAX11612–
MAX11617 are guaranteed over the extended tempera-
ture range (-40°C to +85°C). For pin-compatible 10-bit
parts, refer to the MAX11606–MAX11611 data sheet. For
pin-compatible 8-bit parts, refer to the MAX11600–
MAX11605 data sheet.
Applications
Handheld Portable
Applications
Solar-Powered Remote
Systems
Medical Instruments
Battery-Powered Test
Equipment
Received-Signal-Strength
Indicators
System Supervision
Features
o High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
o Single-Supply
2.7V to 3.6V (MAX11613/MAX11615/MAX11617)
4.5V to 5.5V (MAX11612/MAX11614/MAX11616)
o Internal Reference
2.048V (MAX11613/MAX11615/MAX11617)
4.096V (MAX11612/MAX11614/MAX11616)
o External Reference: 1V to VDD
o Internal Clock
o 4-Channel Single-Ended or 2-Channel Fully
Differential (MAX11612/MAX11613)
o 8-Channel Single-Ended or 4-Channel Fully
Differential (MAX11614/MAX11615)
o 12-Channel Single-Ended or 6-Channel Fully
Differential (MAX11616/MAX11617)
o Internal FIFO with Channel-Scan Mode
o Low Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down Mode
o Software-Configurable Unipolar/Bipolar
o Small Packages
8-Pin µMAX (MAX11612/MAX11613)
16-Pin QSOP (MAX11614–MAX11617)
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
I2C SLAVE
ADDRESS
MAX11612EUA+ -40°C to +85°C 8 µMAX
0110100
MAX11613EUA+ -40°C to +85°C 8 µMAX
0110100
MAX11614EEE+* -40°C to +85°C 16 QSOP 0110011
MAX11615EEE+* -40°C to +85°C 16 QSOP
MAX11616EEE+* -40°C to +85°C 16 QSOP
0110011
0110101
MAX11617EEE+* -40°C to +85°C 16 QSOP 0110101
+Denotes a lead(Pb)-free/RoHs-compliant package.
*Future product—contact factory for availability.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Pin Configurations, Typical Operating Circuit, and Selector
Guide appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

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MAX11613 pdf
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel, 2-Wire Serial, 12-Bit ADCs
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD = 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF = 2.048V
(MAX11613/MAX11615/MAX11617), VREF = 4.096V (MAX11612/MAX11614/MAX11616), fSCL = 1.7MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 12)
Serial-Clock Frequency
fSCLH (Note 13)
1.7 MHz
Hold Time, Repeated START
Condition (Sr)
tHD, STA
160 ns
Low Period of the SCL Clock
High Period of the SCL Clock
tLOW
tHIGH
320 ns
120 ns
Setup Time for a Repeated START
Condition (Sr)
tSU, STA
160 ns
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
tHD, DAT (Note 10)
tSU, DAT
tRCL
0 150 ns
10 ns
20 80 ns
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1 Measured from 0.3VDD - 0.7VDD
20 160 ns
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
tFCL
tRDA
tFDA
tSU, STO
CB
tSP
Measured from 0.3VDD - 0.7VDD
Measured from 0.3VDD - 0.7VDD
Measured from 0.3VDD - 0.7VDD (Note 11)
(Notes 10 and 13)
20
20
20
160
0
80 ns
160 ns
160 ns
ns
400 pF
10 ns
Note 1: For DC accuracy, the MAX11612/MAX11614/MAX11616 are tested at VDD = 5V and the MAX11613/MAX11615/MAX11617
are tested at VDD = 3V. All devices are configured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit).
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVP-P.
Note 9: Measured as for the MAX11613/MAX11615/MAX11617:
[ ]
VFS(3.6V) VFS(2.7V)
⎣⎢
×
2N
1
VREF ⎦⎥
(3.6V 2.7V)
_______________________________________________________________________________________ 5

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MAX11613 arduino
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel, 2-Wire Serial, 12-Bit ADCs
swing from (GND - 0.3V) to (VDD + 0.3V) without caus-
ing damage to the device. For accurate conversions,
the inputs must not go more than 50mV below GND or
above VDD.
Single-Ended/Differential Input
The SGL/DIF of the configuration byte configures the
MAX11612–MAX11617 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are
the difference between the analog input selected by
CS[3:0] and GND (Table 3). In differential mode (SGL/
DIF = 0), the digital conversion results are the differ-
ence between the + and the - analog inputs selected
by CS[3:0] (Table 4).
Unipolar/Bipolar
When operating in differential mode, the BIP/UNI bit of
the set-up byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to VREF. A negative differential analog
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±VREF/2. The digital output code is bina-
ry in unipolar mode and two’s complement in bipolar
mode. See the Transfer Functions section.
In single-ended mode, the MAX11612–MAX11617 al-
ways operates in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to VREF.
2-Wire Digital Interface
The MAX11612–MAX11617 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock line
(SCL). SDA and SCL facilitate bidirectional communica-
tion between the MAX11612–MAX11617 and the master
at rates up to 1.7MHz. The MAX11612–MAX11617 are
slaves that transfer and receive data. The master (typi-
cally a microcontroller) initiates data transfer on the bus
and generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the Typical
Operating Circuit). Series resistors (RS) are optional. They
protect the input architecture of the MAX11612–
MAX11617 from high voltage spikes on the bus lines and
minimize crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX11612–MAX11617.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is
high. The master terminates a transmission with a
STOP condition (P), a low-to-high transition on SDA
while SCL is high (Figure 5). A repeated START condi-
tion (Sr) can be used in place of a STOP condition to
leave the bus active and the interface mode
unchanged (see the HS Mode section).
S Sr
P
SDA
SCL
Figure 5. START and STOP Conditions
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX11612–MAX11617 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not-acknowledge,
the receiver allows SDA to be pulled high before the
rising edge of the acknowledge-related clock pulse
and leaves SDA high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
S
SDA
SCL
12
NOT ACKNOWLEDGE
ACKNOWLEDGE
89
Figure 6. Acknowledge Bits
______________________________________________________________________________________ 11

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