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PDF MAX11602 Data sheet ( Hoja de datos )
| Número de pieza | MAX11602 | |
| Descripción | (MAX11600 - MAX11605) 2-Wire Serial 8-Bit ADCs | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-4554; Rev 0; 4/09
www.DataSheet4U.com
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
General Description
The MAX11600–MAX11605 low-power, 8-bit, multichan-
nel, analog-to-digital converters (ADCs) feature internal
track/hold (T/H), voltage reference, clock, and an
I2C-compatible 2-wire serial interface. These devices
operate from a single supply and require only 350µA at
the maximum sampling rate of 188ksps. Auto-
Shutdown™ powers down the devices between conver-
sions, reducing supply current to less than 1µA at low
throughput rates. The MAX11600/MAX11601 provide 4
analog input channels each, the MAX11602/MAX11603
provide 8 analog input channels each while the
MAX11604/MAX11605 provide 12 analog input channels.
The analog inputs are software configurable for unipolar or
bipolar and single-ended or pseudo-differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX11601/
MAX11603/MAX11605 feature a 2.048V internal refer-
ence and the MAX11600/MAX11602/MAX11604 feature
a 4.096V internal reference.
The MAX11600/MAX11601 are available in 8-pin SOT23
packages. The MAX11602–MAX11605 are available in
16-pin QSOP packages. The MAX11600–MAX11605 are
guaranteed over the extended industrial temperature
range (-40°C to +85°C). Refer to the MAX11606–
MAX11611 for 10-bit devices and to the MAX11612–
MAX11617 for 12-bit devices.
Applications
Handheld Portable Applications
Medical Instruments
Battery-Powered Test Equipment
Solar-Powered Remote Systems
Received-Signal-Strength Indicators
System Supervision
Features
o High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
o Single Supply
2.7V to 3.6V (MAX11601/MAX11603/MAX11605)
4.5V to 5.5V (MAX11600/MAX11602/MAX11604)
o Internal Reference
2.048V (MAX11601/MAX11603/MAX11605)
4.096V (MAX11600/MAX11602/MAX11604)
o External Reference: 1V to VDD
o Internal Clock
o 4-Channel Single-Ended or 2-Channel Pseudo-
Differential (MAX11600/MAX11601)
o 8-Channel Single-Ended or 4-Channel Pseudo-
Differential (MAX11602/MAX11603)
o 12-Channel Single-Ended or 6-Channel Pseudo-
Differential (MAX11604/MAX11605)
o Internal FIFO with Channel-Scan Mode
o Low Power
350µA at 188ksps
110µA at 75ksps
8µA at 10ksps
1µA in Power-Down Mode
o Software Configurable Unipolar/Bipolar
o Small Packages
8-Pin SOT23 (MAX11600/MAX11601)
16-Pin QSOP (MAX11602–MAX11605)
Pin Configurations and Typical Operating Circuit appear
at end of data sheet.
Ordering Information/Selector Guide
PART
TEMP RANGE PIN-PACKAGE
TUE
(LSB)
MAX11600EKA+ -40°C to +85°C
8 SOT23
±2
MAX11601EKA+ -40°C to +85°C
8 SOT23
±2
MAX11602EEE+* -40°C to +85°C
16 QSOP
±1
MAX11603EEE+
-40°C to +85°C
16 QSOP
±1
MAX11604EEE+* -40°C to +85°C
16 QSOP
±1
MAX11605EEE+* -40°C to +85°C
16 QSOP
±1
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Future product—contact factory for availability.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
INPUT
CHANNELS
4
4
8
8
12
12
INTERNAL
REFERENCE (V)
4.096
2.048
4.096
2.048
4.096
2.048
TOP
MARK
AAJE
AAJG
—
—
—
—
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), VDD = 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
VREF = 2.048V (MAX11601/MAX11603/MAX11605), VREF = 4.096V (MAX11600/MAX11602/MAX11604). External clock, fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
SYMBOL
tHD.DAT (Note 12)
tSU.DAT
tRCL (Note 13)
CONDITIONS
MIN TYP MAX UNITS
0 150 ns
10 ns
20 80 ns
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1 (Note 13)
20 160 ns
Fall Time of SCL Signal
tFCL (Note 13)
20 80 ns
Rise Time of SDA Signal
tRDA (Note 13)
20 160 ns
Fall Time of SDA Signal
tFDA (Note 13)
20 160 ns
Setup Time for STOP Condition
tSU, STO
160 ns
Capacitive Load for Each Bus Line CB
400 pF
Pulse Width of Spike Suppressed
tSP
0 10 ns
Note 1: The MAX11600/MAX11602/MAX11604 are tested at VDD = 5V and the MAX11601/MAX11603/MAX11605 are tested at VDD
= 3V. All devices are configured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Ground on channel; sine wave applied to all off channels.
Note 5: Conversion time is defined as the number of clock cycles (eight) multiplied by the clock period. Conversion time does not
include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 7: When AIN_/REF (MAX11600/MAX11601/MAX11604/MAX11605) or REF (MAX11602/MAX11603) is configured to be an inter-
nal reference (SEL[2:1] = 11), decouple AIN_/REF or REF to GND with a 0.01µF capacitor.
Note 8: The switch connecting the reference buffer to AIN_/REF or REF has a typical on-resistance of 675Ω.
Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mVP-P.
Note 10: Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX). For operation beyond this range, see the Typical
Operating Characteristics.
Note 11: Power-supply rejection ratio is measured as:
[ ]VFS (3.3V) − VFS (2.7V)
×
2N
VREF
3.3V − 2.7V
,
for the MAX11601/MAX11603/MAX11605, where N is the number of bits.
Power-supply rejection ratio is measured as:
[ ]VFS (5.5V) − VFS (4.5V)
×
2N
VREF
5.5V − 4.5V
,
for the MAX11600/MAX11602/MAX11604, where N is the number of bits.
Note 12: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of
SCL’s falling edge (Figure 1).
Note 13: CB = total capacitance of one bus line in pF. tR, tFDA, and tF measured between 0.3VDD and 0.7VDD. The minimum value is
specified at TA = +25°C with CB = 400pF.
Note 14: fSCLH must meet the minimum clock low time plus the rise/fall times.
_______________________________________________________________________________________ 5
5 Page 
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
Table 1. Setup Byte Format
BIT 7
(MSB)
REG
BIT 6
SEL2
BIT 5
SEL1
BIT 4
SEL0
BIT 3
CLK
BIT 2
BIP/UNI
BIT 1
RST
BIT 0
(LSB)
X
BIT NAME
DESCRIPTION
7
REG
Register bit. 1 = setup byte, 0 = configuration byte (Table 2).
6
SEL2
Three bits select the reference voltage and the state of AIN_/REF
5
SEL1
(MAX11600/MAX11601/MAX11604/MAX11605) or REF (MAX11602/MAX11603) (Table 6).
4
SEL0
Default to 000 at power-up.
3
CLK
1 = external clock, 0 = internal clock. Defaulted to zero at power-up.
2
BIP/UNI
1 = bipolar, 0 = unipolar. Defaulted to zero at power-up (see the Unipolar/Bipolar section).
1 RST 1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
0 X Don’t care; can be set to 1 or 0.
Single-Ended/Pseudo-Differential Input
The SGL/DIF bit of the configuration byte configures the
MAX11600–MAX11605 analog input circuitry for single-
ended or pseudo-differential inputs (Table 2). In single-
ended mode (SGL/DIF = 1), the digital conversion results
are the difference between the analog input selected by
CS[3:0] and GND (Table 3). In pseudo-differential mode
(SGL/DIF = 0), the digital conversion results are the differ-
ence between the positive and the negative analog inputs
selected by CS[3:0] (Table 4). The negative analog input
signal must remain stable within ±0.5 LSB (±0.1 LSB for
best results) with respect to GND during a conversion.
Unipolar/Bipolar
When operating in pseudo-differential mode, the BIP/
UNI bit of the setup byte (Table 1) selects unipolar or
bipolar operation. Unipolar mode sets the differential
analog input range from zero to VREF. A negative differ-
ential analog input in unipolar mode causes the digital
output code to be zero. Selecting bipolar mode sets the
differential input range to ±VREF/2, with respect to the
negative input. The digital output code is binary in
unipolar mode and two’s complement binary in bipolar
mode (see the Transfer Functions section).
In single-ended mode, the MAX11600–MAX11605
always operate in unipolar mode regardless of the
BIP/UNI setting, and the analog inputs are internally ref-
erenced to GND with a full-scale input range from zero
to VREF.
Digital Interface
The MAX11600–MAX11605 feature a 2-wire interface
consisting of a serial-data line (SDA) and a serial-clock
line (SCL). SDA and SCL facilitate bidirectional communi-
cation between the MAX11600–MAX11605 and the mas-
ter at rates up to 1.7MHz. The MAX11600–MAX11605 are
slaves that transmit and receive data. The master (typical-
ly a microcontroller) initiates data transfer on the bus and
generates SCL to permit that transfer.
SDA and SCL must be pulled high. This is typically
done with pullup resistors (500Ω or greater) (see
Typical Operating Circuit). Series resistors (RS) are
optional. They protect the input architecture of the
MAX11600–MAX11605 from high-voltage spikes on the
bus lines and minimize crosstalk and undershoot of the
bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data in or out of the MAX11600–MAX11605. The data
on SDA must remain stable during the high period of
the SCL clock pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). Both SDA and SCL idle high when
the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP
condition (P), a low-to-high transition on SDA, while
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MAX11602.PDF ] | |
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