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PDF NJU3426 Data sheet ( Hoja de datos )

Número de pieza NJU3426
Descripción 16 segments 14 digits / QFP48-P1
Fabricantes JRC 
Logotipo JRC Logotipo



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NJU3426
16-SEGMENT X 14-Digit
VFD CONTROLLER / DRIVER
GENERAL DESCRIPTION
The NJU3426 is a VFD (Vacuum Fluorescent Display)
controller/driver to dynamically drive up to 16 segments x 14
digits. It consists of display data RAM, an address counter,
command registers, a serial interface and high voltage drivers.
The NJU3426 features the direct connection to MPU and the
high voltage drivers of 45V well-suited for various VFD
displays.
PACKAGE OUTLINE
NJU3426FP1
FEATURES
Directly Drives 16-segment x 14-digit
High VFD Driving Voltage
Display Shift Function
: |VDD-VFDP|45V
Programmable Duty Ratio for Timing Signal
:2/16, 4/16, 6/16, 8/16, 10/16, 12/16, 14/16, 15/16 duty
Display ON/OFF Control Function
Display Data RAM
: 30 x 8-bit
Built-in Oscillator (External Ceramic Resonator or External Resistor or External Clock)
8-bit Serial Interface
Power-ON Reset Function
Operating Voltage
: 3.3V / 5.0V
C-MOS Technology
Package Outline
:QFP48-P1
BLOCK DIAGRAM
S0 to S15
T0 to T13
VDD
VSS
VFDP
High Voltage Driver
Segment Data Latch
High Voltage Driver
Timing Counter
Display RAM
30 x8-bit
Duty
Counter
Timing
Counter
Instruction Decoder
OSC XT
XTb
SI
SCK Serial Buffer
CSb
REST
RSTb
Ver.2003-09-02
-1-

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NJU3426
(3) COMMAND REGISTER 2
The “Command register 2” is used for setting the “Initial character address”, which corresponds to the T0 pin. When
the upper 2 bits (B7 and B6) of the 1st word is “0,1”, the lower 4 bits (B3 to B0) are interpreted as command data and
stored in the “Command register 2”. The contents of the “Command register 2” are initialized to the default values by
the power-ON reset or the reset signal, as shown below.
DEFAULT VALUES OF COMMAND REGISTER 2
Initial character address : C1 (0,0,0,1)
B7 B6 B5 B4 B3 B2 B1 B0
0 1 * * DS3 DS2 DS1 DS0
Recognition data
Initial character address
*:don’t care
DS3 DS2 DS1 DS0
0 000
0 001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Initial character address
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
Prohibited
Ver.2003-09-02
-5-

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NJU3426
DC characteristics 2
(VDD=3.3V, VSS=0V, Ta=-40 to 85°C)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNIT
Operating voltage
“H” level input voltage
“L” level input voltage
Input off leak current
Display output current
VDD VDD terminal
VIH XT, RSTb, CSb, SCK, SI terminals
VIL
IIZ
CSb, SCK, SI terminals
VDD=3.6V, VI=0 or 3.6V
S0 to S15
VDD=3.0V,
IOH
terminals
T0 to T13
VFDP=VDD-40V,
VOH=VDD-1.5V
terminals
3.0
0.8VDD
3.6
0.2VDD
±1
V
V
µA
-2 -4
mA
-4.5 -9
mA
Pull-up resistance
Pull-down resistance
RUR
RDST
RSTb terminal, Ta=25°C, VI=VSS
S0 to S15, T0 to T13 terminals, Ta=25°C
VI=VDD, VFDP=VDD-40V
VSS terminal,
All Segment/Timing output terminals
100
60
280 k
160 k
Logic operating current
ISS
open, RSTb terminal open,
Ceramic resonator:1MHz,
0.8 1.5 mA
All Segment output OFF and All Timing
output OFF
Display operating
current
VFDP terminal, VFDP=VDD-40V,
IFDP Ceramic resonator:1MHz,
All Segment/Timing output ON
10 15 mA
AC characteristics 2
PARAMETER
Operating oscillation frequency
CR oscillation frequency *
External clock Input
Rise time, Fall time
Serial input data setup time
Serial input data hold time
Serial clock frequency
Serial clock interval time
Reset palse width
Power rise time
SYMBOL
fXT
fCR
tCLH, tCLL
tSIS
tSIH
fSCK
tSCI
tRSTb
tR
CONDITIONS
Fig. 1
Ta=25°C
Rf=18k
Fig. 2
Fig. 2
Fig. 2
Fig. 3
Fig. 3
Fig. 4
Fig. 5
(VDD=3.3V, VSS=0V, Ta=-40 to 85°C)
MIN TYP MAX UNIT
0.8 2 MHZ
0.85 1 1.15 MHz
250 *) ns
70 ns
70 ns
0.8 MHZ
10 µs
20 µs
0.05 5 ms
*) Noises on SCK during rise time or fall time may cause malfunctions. Testing samples in the application is recommended.
Ver.2003-09-02
- 11 -

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