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PDF SE98A Data sheet ( Hoja de datos )

Número de pieza SE98A
Descripción DDR Memory Module Temp Sensor
Fabricantes NXP Semiconductors 
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SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
Rev. 01 — 5 March 2009
Product data sheet
www.datasheet4u.com
1. General description
The NXP Semiconductors SE98A measures temperature from 40 °C and +125 °C with
JEDEC Grade B ±1 °C accuracy between +75 °C and +95 °C communicating via the
I2C-bus/SMBus. It is typically mounted on a Dual In-Line Memory Module (DIMM)
measuring the DRAM temperature in accordance with the new JEDEC (JC-42.4) Mobile
Platform Memory Module Thermal Sensor Component specification.
The SE98A thermal sensor operates over the VDD range of 1.7 V to 3.6 V. The SE98A
does not include the 2 k SPD and is designed for custom DIMM where larger SPD is
required.
The Temp Sensor (TS) consists of an Analog-to-Digital Converter (ADC) that monitors
and updates its own temperature readings 8 times per second, converts the reading to a
digital data, and latches them into the data temperature registers. User-programmable
registers, such as Shutdown or Low-power modes and the specification of temperature
event and critical output boundaries, provide flexibility for DIMM temperature-sensing
applications.
When the temperature changes beyond the specified boundary limits, the SE98A outputs
an EVENT signal. The user has the option of setting the EVENT output signal polarity as
either an active LOW or active HIGH comparator output for thermostat operation, or as a
temperature event interrupt output for microprocessor-based systems. The EVENT output
can even be configured as a critical temperature output.
The SE98A supports the industry-standard 2-wire I2C-bus/SMBus serial interface. The
SMBus TIMEOUT function is supported to prevent system lock-ups. Manufacturer and
Device ID registers provide the ability to confirm the identify of the device. Three address
pins allow up to eight devices to be controlled on a single bus.
The SE98A is an improved SE98 and is comparable to the thermal sensor in the SE97 but
with voltage range of 1.7 V to 3.6 V.
2. Features
I JEDEC (JC-42.4) DIMM temperature sensor
I Optimized for voltage range: 1.7 V to 3.6 V
I Shutdown current: 0.1 µA (typ.) and 5.0 µA (max.)
I 2-wire interface: I2C-bus/SMBus compatible, 0 Hz to 400 kHz
I SMBus ALERT and TIMEOUT (programmable)
I ESD protection exceeds 2000 V HBM per JESD22-A114, 250 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

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SE98A pdf
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7. Functional description
www.datasheet4u.com
7.1 Serial bus interface
The SE98A uses the 2-wire serial bus (I2C-bus/SMBus) to communicate with a host
controller. The serial bus consists of a clock (SCL) and data (SDA) signals. The device
can operate on either the I2C-bus Standard/Fast mode or SMBus. The I2C-bus
Standard-mode is defined to have bus speeds from 0 Hz to 100 kHz, I2C-bus Fast-mode
from 0 Hz to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master
generates the SCL signal, and the SE98A uses the SCL signal to receive or send data on
the SDA line. Data transfer is serial, bidirectional, and is one bit at a time with the Most
Significant Bit (MSB) transferred first, and a complete I2C-bus data is 1 byte. Since SCL
and SDA are open-drain, pull-up resistors must be installed on these pins.
7.2 Slave address
The SE98A uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave address
that allows a total of eight devices to coexist on the same bus. The input of each pin is
sampled at the start of each I2C-bus/SMBus access. The A0, A1 and A2 pins are pulled
LOW internally. The A0 pin is also overvoltage tolerant, supporting 10 V software write
protection when applied to the SPD that shares common address lines.
Fig 5. Slave address
MSB
00
slave address
R/W
LSB
1 1 A2 A1 A0 X
fixed
hardware
selectable
002aab304
SE98A_1
Product data sheet
Rev. 01 — 5 March 2009
© NXP B.V. 2009. All rights reserved.
5 of 42

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SE98A arduino
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
www.datasheet4u.com
7.6 Device initialization
SE98A temperature sensors have programmable registers, which, upon power-up, default
to zero. The open-drain EVENT output is default to being disabled, comparator mode and
active LOW. The alarm trigger registers default to being unprotected. The configuration
registers, upper and lower alarm boundary registers and critical temperature window are
defaulted to zero and need to be programmed to the desired values. SMBus TIMEOUT
feature defaults to being enabled and can be programmed to disable. These registers are
required to be initialized before the device can properly function. Except for the SPD,
which does not have any programmable registers, and does not need to be initialized.
Table 4 shows the default values and the example value to be programmed to these
registers.
Table 4. Registers to be initialized
Register Default value Example value
01h 0000h
0209h
02h 0000h
03h 0000h
04h 0000h
22h 0000h
0550h
1F40h
05F0h
0000h
Description
Configuration register
hysteresis = 1.5 °C
EVENT output = Interrupt mode
EVENT output is enabled
Upper Boundary Alarm Trip register = 85 °C
Lower Boundary Alarm Trip register = 20 °C
Critical Alarm Trip register = 95 °C
SMBus register = no change
7.7 SMBus Time-out
The SE98A supports the SMBus time-out feature. If the host holds SCL LOW between
25 ms and 35 ms, the SE98A would reset its internal state machine to the bus idle state to
prevent the system bus hang-up. This feature is turned on by default. The SMBus time-out
is disabled by writing a logic 1 to bit 7 of register 22h.
Remark: When SMBus time-out is enabled, the I2C-bus minimum bus speed is limited by
the SMBus time-out timer, and goes down to only 10 kHz.
The SE98A has no SCL driver, so it cannot hold the SCL line LOW.
7.8 SMBus ALERT
The SE98A supports SMBus ALERT when it is programmed for the Interrupt mode and
when the EVENT polarity bit is set to logic 0. The EVENT pin can be ANDed with other
EVENT or ALERT signals from other slave devices to signal their intention to
communicate with the host controller. When the host detects EVENT or ALERT signal
LOW, it issues an Alert Response Address (ARA) to which a slave device would respond
with its address. When there are multiple slave devices generating an ALERT the SE98A
performs bus arbitration. If it wins the bus, it responds to the ARA and then clears the
EVENT pin.
Remark: Either in comparator mode or when the SE98A crosses the critical temperature,
the host must also read the EVENT status bit and provide remedy to the situation by
bringing the temperature to within the alarm window or below the critical temperature if
that bit is set. Otherwise, the EVENT pin will not get de-asserted.
SE98A_1
Product data sheet
Rev. 01 — 5 March 2009
© NXP B.V. 2009. All rights reserved.
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