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PDF PE43703 Data sheet ( Hoja de datos )

Número de pieza PE43703
Descripción RF Digital Attenuator 7-bit
Fabricantes Peregrine Semiconductor 
Logotipo Peregrine Semiconductor Logotipo



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Product Description
wwTwh.deataPshEe4et347u.0co3mis a HaRP-enhanced, high linearity, 7-bit RF
Digital Step Attenuator (DSA). This highly versatile DSA
covers a 31.75 dB attenuation range in 0.25 dB, 0.5 dB, or 1.0
dB steps. The customer can choose which step size and
associated specifications are best suited for their application.
The Peregrine 50RF DSA provides multiple CMOS control
interfaces and an optional external Vss feature. It maintains
high attenuation accuracy over frequency and temperature and
exhibits very low insertion loss and low power consumption.
Performance does not change with Vdd due to on-board
regulator. This next generation Peregrine DSA is available in a
5x5 mm 32-lead QFN footprint.
The PE43703 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Package Type
32-lead 5x5x0.85 mm QFN Package
Product Specification
PE43703
50 RF Digital Attenuator
7-bit, 31.75 dB, DC-6.0 GHz, VssEXT option
Features
HaRP™-enhanced UltraCMOS™ device
Attenuation options: 0.25 dB, 0.5 dB, or
1.0 dB steps to 31.75 dB
0.25 dB monotonicity for 4.0 GHz
0.5 dB monotonicity for 5.0 GHz
1 dB monotonicity for 6.0 GHz
High Linearity: Typical +59 dBm IIP3
Excellent low-frequency performance
Optional External Vss Control (VssEXT)
3.3 V or 5.0 V Power Supply Voltage
Fast switch settling time
Programming Modes:
Direct Parallel
Latched Parallel
Serial-Addressable: Program up to
eight addresses 000 - 111
High-attenuation state @ power-up (PUP)
CMOS Compatible
No DC blocking capacitors required
Figure 2. Functional Schematic Diagram
RF Input
Switched Attenuator Array
RF Output
Parallel Control 7
Serial In
CLK
LE
Control Logic Interface
A0 A1 A2
Document No. 70-0245-04 www.psemi.com
(optional)
P/S VssEXT
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15

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PE43703 pdf
PE43703
Product Specification
Performance Plots, 1 dB state (continued)
Figure 15. 1 dB Attenuation Error vs. Frequency
www.datasheet4u.co3m000 MHz
1.500
4000 MHz
5000 MHz
6000 MHz
1.000
0.500
0.000
-0.500
-1.000
-1.500
0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0
Atte nuation Setting (dB.)
Figure 17. Input Return Loss vs. Attenuation
T = +25C
0dB
0.25dB
0.5dB
1dB
2dB
4dB
8dB
16dB
31.75dB
0
-10
-20
-30
-40
-50
-60
-70
0123456789
Frequency (GHz.)
Figure 19. Input Return Loss vs. Temperature
16dB State
-40C 25C 85C
0
-5
-10
-15
-20
-25
-30
-35
-40
01234 56789
Frequency (GHz.)
Document No. 70-0245-04 www.psemi.com
Figure 16. Insertion Loss vs. Temperature
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
0.0
-40C
+25C
+85C
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
Frequency (GHz)
9.0
Figure 18. Output Return Loss vs. Attenuation
T = +25C
0dB
4dB
0
0.25dB
8dB
0.5dB
16dB
1dB
31.75dB
2dB
-10
-20
-30
-40
-50
-60
0 1 23 45 6 7 89
Frequency (GHz.)
Figure 20. Output Return Loss vs. Temperature
16dB State
-40C 25C 85C
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
01 23 45 67 89
Frequency (GHz.)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 15

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PE43703 arduino
PE43703
Product Specification
Figure 29. Serial-Addressable Timing Diagram
Bits can either be set to logic high or logic low
DI[6:0]
TDISU
wwwAD.dDa[2t:a0s] heet4uVA.LcIDom
TASU
P/S
TPSSU
SI D[0] D[1] D[2] D[3] D[4] D[5] D[6]
TSISU
TSIH
CLK
TCLKL
TCLKH
LE
A[0] A[1] A[2]
DO[6:0]
TDIH
TAH
TPSH
TLESU
TLEPW
TPD
VALID
Figure 30. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
DI[6:0]
LE
DO[6:0]
TPSSU
VALID
TDISU
TPSH
TDIH
TLEPW
VALID
TDIPD
TPD
Table 13. Serial Interface AC Characteristics
VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min Max Unit
FCLK
TCLKH
TCLKL
Serial clock frequency
Serial clock HIGH time
Serial clock LOW time
- 10 MHz
30 - ns
30 - ns
TLESU
Last serial clock rising edge
setup time to Latch Enable
rising edge
10 - ns
TLEPW Latch Enable min. pulse width 30
-
TSISU Serial data setup time
10 -
TSIH Serial data hold time
10 -
TDISU Parallel data setup time
100 -
TDIH Parallel data hold time
100 -
TASU Address setup time
100 -
TAH Address hold time
100 -
TPSSU Parallel/Serial setup time
100 -
TPSH Parallel/Serial hold time
100 -
TPD Digital register delay (internal) - 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked
at 10 MHz to verify fclk specification.
Document No. 70-0245-04 www.psemi.com
Table 14. Parallel and Direct Interface AC
Characteristics
VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min Max Unit
TLEPW
Latch Enable minimum
pulse width
30 - ns
TDISU
Parallel data setup time
100 -
ns
TDIH Parallel data hold time
100 -
ns
TPSSU
Parallel/Serial setup time
100 -
ns
TPSIH
TPD
TDIPD
Parallel/Serial hold time
Digital register delay
(internal)
Digital register delay
(internal, direct mode only)
100 -
- 10
-5
ns
ns
ns
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
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