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PDF EM28C1602C3FL Data sheet ( Hoja de datos )

Número de pieza EM28C1602C3FL
Descripción Flash and SRAM Combo Memory
Fabricantes NanoAmp Solutions 
Logotipo NanoAmp Solutions Logotipo



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No Preview Available ! EM28C1602C3FL Hoja de datos, Descripción, Manual

EM28C1602C3FL
NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
EM28C1602C3FL
Advance Information
Low Voltage, Extended Temperature
FLASH AND SRAM COMBO MEMORY
www.datasheet4u.com
FEATURES
• Organization: 1,048K x 16 (Flash)
128K x 16 (SRAM)
• Basic configuration:
Flash
Thirty-nine erase blocks
– Eight 4K-word parameter blocks
– Thirty-one 32K-word main memory blocks
SRAM
2Mb SRAM for data storage
– 128K-words
• F_VCC, F_VPP, S_VCC voltages
2.7V (MIN)/3.3V (MAX) F_VCC read voltage
2.7V (MIN)/3.3V (MAX) S_VCC read voltage
1.8V (TYP) F_VPP (in-system PROGRAM/ERASE)
12V ±5% (HV) F_VPP (production programming
compatibility)
1.0V (MIN) S_VCC (SRAM data retention)
• Asynchronous access time
Flash access time: 90ns @ 2.7V F_VCC
SRAM access time: 85ns @ 2.7V S_VCC
• Low power consumption
• Enhanced WRITE/ERASE suspend option
• Read/Write SRAM during program/erase of Flash
• 128-bit chip OTP protection register for security
purposes
• Cross-compatible command set support
• PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
BALL ASSIGNMENT
66-Ball FBGA (Top View)
1 2 3 4 5 6 7 8 9 10 11 12
A NC NC NC A11 A15 A14 A13 A12 F_Vss NC NC NC
B A16 A8
A10 A9 DQ15 S_W E# DQ14 DQ7
C F_WE # NC
DQ13
DQ6 DQ4 DQ5
D S_Vss F_RP#
DQ12 S_CE2 S_Vcc F_Vcc
E F_WP # F_Vpp
A19 DQ11
DQ10
DQ2 DQ3
F S_L B# S_UB# S_OE #
DQ9 DQ8 DQ0 DQ1
G A18 A17 A7 A6 A3 A2 A1 S_CE1#
H NC NC NC A5 A4 A0 F_CE# F_Vss F_OE# NC NC NC
OPTIONS
• Timing
90ns
MARKING
-90
• Boot Block
Top
Bottom
T
B
• Operating Temperature Range
Extended Temperature (-40oC to +85oC)
ET
• Package
66-ball FBGA (8 x 8 grid)
FL
Part Number Example:
EM28C1602C3FL-90 TET
Stock No. 23134-A 1/01
1
Advance - Subject to Change without Notice

1 page




EM28C1602C3FL pdf
NanoAmp Solutions, Inc.
EM28C1602C3FL
Advance
BALL DESCRIPTIONS (continued)
66-BALLFBGA
NUMBERS
E4
SYMBOL
F_VPP
www.datasheet4u.com
D10
A9, H8
D9
D3
A1, A2, A3,
A10, A11, A12,
C4, H1, H2, H3,
H10, H11, H12
F_VCC
F_VSS
S_VCC
S_VSS
NC
TYPE
Input/
Supply
Supply
Supply
Supply
Supply
DESCRIPTION
Flash Program/Erase Power Supply: [1.65V–3.3V or 11.4V–12.6V]. Operates
as input at logic levels to control complete device protection. Provides
backward compatibility for factory programming when driven to 11.4V–
12.6V. Lower F_VPP voltages are available; consult factory for availability.
Flash Power Supply: [2.7V–3.3V]. Supplies power for device operation.
Flash Specific Ground: Do not float any ground pin.
SRAM Power Supply: [2.7V–3.3V]. Supplies power for device operation.
SRAM Specific Ground: Do not float any ground pin.
No Connect: Lead is not internally connected; it may be driven or
floated.
Stock No. 23134-A 1/01
5
Advance - Subject to Change without Notice

5 Page





EM28C1602C3FL arduino
NanoAmp Solutions, Inc.
EM28C1602C3FL
Advance
given READ cycle. Latching the data prevents errors from
occurring if the register input changes during a status
register read. To ensure that the status register output
contains updated status data, CE# or OE# must be toggled
for each subsequent STATUS READ.
The status register provides the internal state of the
wwWwS.dMatatoshteheet4eux.cteormnal microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 7 defines the status
register bits.
After monitoring the status register during a
PROGRAM/ERASE operation, the data appearing on
DQ0–DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be issued
to the CSM.
COMMAND STATE MACHINE OPERATIONS
The CSM decodes instructions for the commands
listed in Table 2. The 8-bit command code is input to the
device on DQ0–DQ7 (see Table 3 for command defini-
tions). During a PROGRAM or ERASE cycle, the CSM
informs the WSM that a PROGRAM or ERASE cycle has
been requested.
During a PROGRAM cycle, the WSM controls the
program sequences and the CSM responds to a PRO-
GRAM SUSPEND command only.
During an ERASE cycle, the CSM responds to an
ERASE SUSPEND command only. When the WSM has
completed its task, the WSMS bit (SR7) is set to a logic HIGH
level and the CSM responds to the full command set. The
CSM stays in the current command state until the micro-
processor issues another command.
The WSM successfully initiates an ERASE or PRO-
GRAM operation only when VPP is within its correct
voltage range.
Table 3
Command Definitions
FIRST CYCLE
COMMAND
OPERATION ADDRESS CSM/INPUT
READ ARRAY
WRITE
X
FFh
IDENTIFYDEVICE
WRITE
X
90h
READ STATUS REGISTER
WRITE
X
70h
WORD PROGRAM
WRITE
X 10h/40h
BLOCK ERASE
WRITE
X
20h
PROGRAM/ERASESUSPEND WRITE
X
B0h
PROGRAM/ERASERESUME WRITE
X
D0h
CLEAR STATUS REGISTER
WRITE
X
50h
SOFTPROTECTION
WRITE
X
0Fh
OTP ENTRY
WRITE
X
AFh
OTPEXIT
WRITE
X
FFh
SECOND CYCLE
OPERATION ADDRESS
READ
WA
READ
IA
READ
BA
WRITE
WA
WRITE
BA
WRITE
WRITE
WRITE
BA
X
X
DATA
AD
ID
SRD
PD
D0h
SPC
AFh
FFh
NOTE: 1. The command data is written through DQ0-DQ7
2. ID = Manufacturer ID: 002Ch; Device ID (Top Boot): 4492h; Device ID (Bottom Boot): 4493h
3. IA = Identify address: 00000h for manufacturer code and 00001h for device code
4. BA = Any address within the block to be selected
5. WA = Word address
6. AD = Array data
7. SRD = Data read from status register
8. PD = Data to be written at location WA
9. SPC = Soft protect command:
00h = Clear all soft protection
FFh = Set all soft protection
F0h = Clear addressed block soft protection
0Fh = Set addressed block soft protection
10. X = Don’t Care
Stock No. 23134-A 1/01
11
Advance - Subject to Change without Notice

11 Page







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