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PDF MAX15025 Data sheet ( Hoja de datos )

Número de pieza MAX15025
Descripción (MAX15024 / MAX15025) High Sink/Source Current Gate Drivers
Fabricantes Maxim Integrated Products 
Logotipo Maxim Integrated Products Logotipo



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No Preview Available ! MAX15025 Hoja de datos, Descripción, Manual

19-1053; Rev 0; 10/07
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
www.datasheet4u.com
General Description
The MAX15024/MAX15025 single/dual, high-speed
MOSFET gate drivers are capable of operating at fre-
quencies up to 1MHz with large capacitive loads. The
MAX15024 includes internal source-and-sink output
transistors with independent outputs allowing for control
of the external MOSFET’s rise and fall time. The
MAX15024 is a single gate driver capable of sinking an
8A peak current and sourcing a 4A peak current. The
MAX15025 is a dual gate driver capable of sinking a 4A
peak current and sourcing a 2A peak current. An inte-
grated adjustable LDO voltage regulator provides gate-
drive amplitude control and optimization.
The MAX15024A/C and MAX15025A/C/E/G accept tran-
sistor-to-transistor (TTL) input logic levels while the
MAX15024B/D and MAX15025B/D/F/H accept CMOS-
input logic levels. High sourcing/sinking peak currents, a
low propagation delay, and thermally enhanced pack-
ages make the MAX15024/MAX15025 ideal for high-fre-
quency and high-power circuits. The MAX15024/
MAX15025 operate from a 4.5V to 28V supply. A sepa-
rate output driver supply input enhances flexibility and
permits a soft-start of the power MOSFETs used in syn-
chronous rectifiers.
The MAX15024/MAX15025 are available in 10-pin
TDFN packages and are specified over the -40°C to
+125°C automotive temperature range.
Applications
Synchronous Rectifier Drivers
Power-Supply Modules
Switching Power Supply
Pin Configurations
TOP VIEW
10 9 8 7 6
MAX15024
EP*
12345
*EP = EXPOSED PAD.
TDFN
Pin Configurations continued at end of data sheet.
Features
o 8A Peak Sink Current/4A Peak Source Current
(MAX15024)
o 4A Peak Sink Current/2A Peak Source Current
(MAX15025)
o Low 16ns Propagation Delay
o 4.5V to 28V Supply Voltage Range
o On-Board Adjustable LDO for Gate-Drive
Amplitude Control and Optimization
o Separate Output Driver Supply
o Independent Source and Sink Outputs (MAX15024)
o Matched Delays Between Inverting and
Noninverting Inputs (MAX15024)
o Matched Delays Between Channels (MAX15025)
o CMOS or TTL Logic-Level Inputs with Hysteresis
for Noise Immunity
o -40°C to +125°C Operating Temperature Range
o Thermal-Shutdown Protection
o 1.95W Thermally Enhanced TDFN Power Packages
Ordering Information
PART
PIN-PACKAGE
PKG
CODE
TOP
MARK
MAX15024AATB+T* 10 TDFN-EP**
MAX15024BATB+T 10 TDFN-EP**
MAX15024CATB+T* 10 TDFN-EP**
MAX15024DATB+T* 10 TDFN-EP**
T1033-1
T1033-1
T1033-1
T1033-1
ATX
ATY
MAX15025AATB+T 10 TDFN-EP** T1033-1
ATZ
MAX15025BATB+T* 10 TDFN-EP**
MAX15025CATB+T* 10 TDFN-EP**
T1033-1
T1033-1
AUA
AUB
MAX15025DATB+T* 10 TDFN-EP** T1033-1 AUC
MAX15025EATB+T* 10 TDFN-EP** T1033-1
MAX15025FATB+T* 10 TDFN-EP** T1033-1
MAX15025GATB+T* 10 TDFN-EP** T1033-1
MAX15025HATB+T* 10 TDFN-EP** T1033-1
Note: All devices are specified over the -40°C to +125°C operating
temperature range.
+Denotes a lead-free package.
*Future product—contact factory for availability.
**EP = Exposed pad. T = Tape and reel.
See the Selector Guide at the end of the data sheet.
Block Diagrams appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX15025 pdf
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
www.daMtasAheXet14u5.c0o2m5 ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = TJ =
+25°C). (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
VCC Undervoltage-Lockout
Hysteresis
300 mV
VCC Undervoltage Lockout to
Output Delay
VCC rising
VCC falling
REG REGULATOR (VCC = 12V, VREG = VDRV, CL = 1µF, FB/SET = GND)
Output Voltage
VREG
12V < VCC < 28V, 0 < ILOAD < 10mA
Dropout Voltage
VR_DO
VCC = 6.5V, ILOAD = 100mA
VCC = 4.5V, ILOAD = 50mA
Load Regulation
VCC = 12V, ILOAD = 0 to 100mA
Line Regulation
12V < VCC < 28V
FB/SET Reference Voltage
External resistive divider connected at
FB/SET
100
2
9 10 11
0.4 0.9
0.2 0.5
1
10
1.10 1.23 1.35
µs
V
V
%
mV
V
FB/SET Threshold
FB/SET Input Leakage Current
DRIVER OUTPUT SINK
VFB rising
VFB = 5.5V
-125
220
+125
mV
nA
Driver Output Resistance
RON-N
VCC = VREG = VDRV = 10V,
sinking 100mA
VCC = VREG = VDRV = 4.5V,
sinking 100mA
(MAX15025E/F/G/H)
TA = +25°C
TA = +125°C
TA = +25°C
TA = +125°C
1.0 1.6
1.25 2.10
1.10 1.65
1.5 2.2
Peak Output Current
Maximum Load Capacitance
IPK-N
OUT_ = 10V
SOA condition: CL x VDRV2 20µJ,
for VDRV = 10V
4A
100 nF
Latchup Robustness
500 mA
DRIVER OUTPUT SOURCE
Driver Output Resistance
RON-P
VCC = VREG = VDRV = 10V,
sourcing 100mA
VCC = VREG = VDRV = 4.5V,
sourcing 100mA
(MAX15025E/F/G/H)
TA = +25°C
TA = +125°C
TA = +25°C
TA = +125°C
1.75 2.50
2.25 3.50
1.85 2.60
2.50 3.75
Peak Output Current
Latchup Robustness
IPK-P
OUT_ = 0V
2A
500 mA
LOGIC INPUTS
Logic 1 Input Voltage
MAX15025A/C/E/G
VIH
MAX15025B/D/F/H
2.0
V
4.25
Logic 0 Input Voltage
MAX15025A/C/E/G
VIL MAX15025B/D/F/H
0.8
V
2
Logic Input Hysteresis
MAX15025A/C/E/G
MAX15025B/D/F/H
0.4
V
1
Logic Input Current Leakage
Input Capacitance
VIN = 18V or GND
-75 +0.01 +75
10
µA
pF
_______________________________________________________________________________________ 5

5 Page





MAX15025 arduino
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
www.datasheet4u.com
Power Dissipation
Power dissipation of the MAX15024/MAX15025 con-
sists of three components: the quiescent current,
capacitive charge and discharge of internal nodes, and
the output current (either capacitive or resistive load).
The sum of these components must be kept below the
maximum power-dissipation limit. The quiescent cur-
rent is 700µA typ. The current required to charge and
discharge the internal nodes is frequency dependent
(see the Typical Operating Characteristics). The
MAX15024/MAX15025 power dissipation when driving
a ground-referenced resistive load is:
P = D x RON(MAX) x ILOAD2
where D is the fraction of the period the MAX15024/
MAX15025s’ output pulls high, RON(MAX) is the maxi-
mum on-resistance of the device with the output high
(p-channel), and ILOAD is the output load current of the
MAX15024/MAX15025. For capacitive loads, the power
dissipation for each driver is:
P = CLOAD x VDRV2 x FREQ
where CLOAD is the capacitive load, VDRV is the driver
supply voltage, and FREQ is the switching frequency.
Layout Information
The MAX15024/MAX15025 MOSFET drivers source and
sink large currents to create very fast rise and fall edges
at the gate of the switching MOSFET. The high di/dt can
cause unacceptable ringing if the trace lengths and
impedances are not well controlled. The following
printed-circuit board (PCB) layout guidelines are recom-
mended when designing with the MAX15024/MAX15025:
• Place one or more 1µF decoupling ceramic capaci-
tor(s) from VDRV to PGND as close to the device as
possible. At least one storage capacitor of 10µF (min)
should be located on the PCB with a low resistance
path to the VCC pin of the MAX15024/MAX15025.
• There are two AC current loops formed between the
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from
gate to source when the gate is being pulled low.
The active current loop is from MOSFET gate to
OUT_ of the MAX15024/MAX15025 to PGND of the
MAX15024/MAX15025, and to the source of the
MOSFET. When the gate of the MOSFET is being
pulled high, the active current loop is from the VDD
terminal of the VDRV terminal of decoupling capaci-
tor, to the VDRV of the MAX15024/MAX15025, to the
OUT_ of the MAX15024/MAX15025, to the MOSFET
gate, to the MOSFET source, and to the negative ter-
minal of the decoupling capacitor. Both charging
current loop and discharging current loop are impor-
tant. It is important to minimize the physical distance
and the impedance in these AC current paths.
• Keep the device as close as possible to the MOSFET.
• In the multilayer PCB, the inner layers should consist
of a GND plane containing the discharging and
charging current loops.
IN+
VIL
P_OUT AND
N_OUT CONNECTED
TOGETHER
OR OUT1/OUT2
Figure 1. Timing Diagram
90%
10%
tD-OFF
tF
VIH
tD-ON
tR
______________________________________________________________________________________ 11

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