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PDF LD3986 Data sheet ( Hoja de datos )
| Número de pieza | LD3986 | |
| Descripción | DUAL ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE REG | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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LD3986
SERIES
DUAL ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE
REG. FOR USE WITH VERY LOW ESR OUT. CAPACITORS
wwsw.dIaNtaPsUheTetV4uO.cLoTmAGE FROM 2.5V TO 6V
s STABLE WITH LOW ESR CERAMIC
CAPACITORS
s ULTRA LOW DROPOUT VOLTAGE (60mV
TYP. AT 150mA LOAD, 0.4mV TYP. AT 1mA
LOAD)
s VERY LOW QUIESCENT CURRENT (155µA
TYP. AT NO LOAD, 290µA TYP. AT 150mA
LOAD; MAX 2µA IN OFF MODE)
s GUARANTEED OUTPUT CURRENT UP TO
150mA FOR BOTH OUTPUTS
s DUAL OUTPUT VOLTAGES
s FAST TURN-ON TIME: TYP. 120µs (CO=1µF,
CBYP=10nF AND IO=1mA)
s LOGIC-CONTROLLED ELECTRONIC
SHUTDOWN
s INTERNAL CURRENT AND THERMAL LIMIT
s OUTPUT LOW NOISE VOLTAGE 30µVRMS
OVER 10Hz to 100KHz
s S.V.R. OF 50dB AT 1KHz, 40dB AT 10KHz
s TEMPERATURE RANGE: -40°C TO 125°C
DESCRIPTION
The LD3986 provides up to 150mA at each output,
from 2.5V to 6V input voltage. The ultra low
drop-voltage, low quiescent current and low noise
Flip-Chip
make it suitable for low power applications and in
battery powered systems. Regulator ground
current increases only slightly in dropout, further
prolonging the battery life. Power supply rejection
is 50 dB at 1KHz and 40 dB at 10KHz. High power
supply rejection is maintained down to low input
voltage levels common to battery operated
circuits. Shutdown Logic Control function is
available for each output, this means that when
the device is used as local regulator, it is possible
to put a part of the board in standby, decreasing
the total power consumption. The LD3986 is
designed to work with low ESR ceramic
capacitors. Typical applications are in mobile
phone and similar battery powered wireless
systems.
Figure 1: Schematic Diagram
September 2005
Rev. 3
1/12
1 page  
LD3986 SERIES
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
CO Output Capacitor
Capacitance
1 22 µF
ESR
0.005
5Ω
Note 1: For VO< 2V, VI=2.5V
Note 2: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specifi-
cation does not apply for input voltages below 2.5V.
Note 3: Enable pin must be driven with a TR = TF < 10ms
Note 4: Turn-on time is time measured between the enable input just exceeding VINH High Value and the output voltage just reaching 95%
of its nominal value
wwNwot.eda5t:aTsyhpeiceat4l tuh.ecrommal protection hysteresis is 20°C
Figure 4: SVR Input Voltage Test Signal
Figure 5: AC Line Regulation Input Voltage Test Signal
5/12
5 Page 
LD3986 SERIES
Table 6: Revision History
Date
07-Dec-2004
06-Jun-2005
22-Sep-2005
Revision
1
2
3
www.datasheet4u.com
Description of Changes
First Release.
Add New Part Number - Table 1.
Order Codes has been updated.
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LD3986.PDF ] | |
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