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PDF LD39300 Data sheet ( Hoja de datos )
| Número de pieza | LD39300 | |
| Descripción | Ultra low drop BICMOS voltage regulator | |
| Fabricantes | STMicroelectronics | |
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LD39300
Ultra low drop BICMOS voltage regulator
Feature summary
■ 3A Guaranteed output current
■ Ultra low dropout voltage (200mV typ. @ 3A
load, 40mV typ. @600mA load)
■ Very low quiescent current (1.2mA typ. @ 3A
load, 1µA max @ 25°C in off mode)
■ Logic-controlled electronic shutdown
■ Current and thermal internal limit
■ ±1.5% Output voltage tolerance @ 25°C
■ Fixed and ADJ output voltages: 1.22V, 1.8V,
2.5V, 3.3V, ADJ. (*see order code)
■ Temperature range: -40 to 125°C
■ Fast dynamic response to line and load
changes
■ Stable with ceramic capacitor (see paragraph
7.1, 7.2, 7.3)
■ Available in PPAK and DPAK
Typical application
■ Microprocessor power supply
■ DSPs power supply
■ Post regulators for switchin suppliers
■ High efficiency linear regulator
PPAK
DPAK
Description
The LD39300 is a fast ultra low drop linear
regulator which operates from 2.5V to 6V input
supply.
A wide range of output options are available. The
low drop voltage, low noise, and ultra low
quiescent current make it suitable for low voltage
microprocessor and memory applications. The
device is developed on a BiCMOS process which
allows low quiescent current operation
independently of output load current.
Order codes
Part numbers
DPAK
LD39300DT12-R
LD39300DT18-R
LD39300DT25-R
LD39300DT33-R
PPAK
LD39300PT18-R
LD39300PT25-R
LD39300PT33-R
LD39300PT-R
January 2007
Rev. 1
Output voltage
1.22V
1.8V
2.5V
3.3V
ADJ From 1.22 to 5.0V
1/17
www.st.com
17
1 page  
LD39300
3 Typical application circuits
Typical application circuits
www.datasheet4u.com (CI and CO Capacitors must be placed as close as possible to the IC pins)
Figure 3. LD39300 Fixed version with inhibit
1 Inhibit Pin is not internally pulled down/up then it must not be left floating. Disable the device
when connected to GND or to a positive voltage less than 0.3V
Figure 4. LD39300 Adjustable version
2 Set R2 as close as possible to 4.7KΩ.
VO = VREF (1 + R1/R2)
5/17
5 Page 
LD39300
7 Application notes
Application notes
7.1www.datasheet4u.com
External capacitors
The LD39300 requires external capacitors for regulator stability. These capacitors must be
selected to meet the requirements of minimum capacitance and equivalent series resistance
(see Figure 14. Figure 15.). The input/output capacitors must be located less than 1cm from
the relative pins and connected directly to the input/output ground pins using traces which
have no other currents flowing through them. Any good quality of Ceramic or Electrolytic
capacitors can be used.
7.2 Input capacitor
An input capacitor whose minimum value is 1µF is required with the LD39300 (amount of
capacitance can be increased without limit). This capacitor must be located a distance of not
more than 1cm from the input pin of the device and returned to a clean analog ground. Any
good quality ceramic, tantalum or film capacitors can be used for this capacitor.
7.3 Output capacitor
It is possible to use Ceramic or Tantalum capacitors but the output capacitor must meet the
requirement for minimum amount of capacitance and E.S.R. (equivalent series resistance)
value. A minimum capacitance of 4.7µF is a good choice to guarantee the stability of the
regulator. Anyway, other CO values can be used according to the (Figure 14. Figure 15.)
showing the allowable ESR range as a function of the output capacitance. This curve
represents the stability region over the full temperature and IO range.
7.4 Thermal note
The output capacitor must maintain its ESR in the stable region over the full operating
temperature range to assure stability. Also, capacitors tolerance and variation with
temperature must be kept in consideration in order to assure the minimum amount of
capacitance at all times.
7.5 Inhibit input operation
The inhibit pin can be used to turn OFF the regulator when pulled down, so drastically
reducing the current consumption down to less than 1µA. When the inhibit feature is not
used, this pin must be tied to VI to keep the regulator output ON at all times. To assure
proper operation, the signal source used to drive the inhibit pin must be able to swing above
and below the specified thresholds listed in the electrical characteristics section (VIH VIL).
The inhibit pin must not be left floating because it is not internally pulled down/up.
11/17
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| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet LD39300.PDF ] | |
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