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PDF TDA8025 Data sheet ( Hoja de datos )
| Número de pieza | TDA8025 | |
| Descripción | IC card interface | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TDA8025 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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TDA8025
IC card interface
Rev. 01 — 6 April 2009
Product data sheet
www.datasheet4u.com
1. General description
The TDA8025 is a cost-effective analog interface for asynchronous smart cards operating
at 3 V, 1.8 V or optionally, 1.2 V. Using few external components, the TDA8025 provides
integrated supply, protection and control functions for a range of applications.
2. Features
I Integrated circuit smart card interface
I 3 V, 1.8 V or 1.2 V smart card supply
I Low power consumption in inactive mode
I Three protected, half duplex, bidirectional buffered input/output lines (C4, C7 and C8)
I VCC regulation:
N 3 V, 1.8 V or optionally 1.2 V at ± 5 % using one 220 nF and one 470 nF low ESR
multilayer ceramic capacitor.
N Current pulse handling for pulses of 40 nAs at VCC = 3 V, 15 nAs at VCC = 1.8 V or
VCC = 1.2 V up to 20 MHz
I Thermal and short-circuit protection for all card contacts
I Automatic activation and deactivation sequences triggered by short-circuit, card
take-off, overheating, falling VDD(INTF) and VDD(INTREGD)
I Enhanced card-side ElectroStatic Discharge (ESD) protection of > 6 kV
I Clock signal using the internal oscillator or an external crystal (≤ 26 MHz) connected to
pin XTAL1
I Card clock generation up to 20 MHz with synchronous frequency changes of fxtal,
1⁄2 fxtal, 1⁄4 fxtal or 1⁄8 fxtal using pins CLKDIV1 and CLKDIV2
I Non-inverted control of pin RST using pin RSTIN
I NDS certified
I Supply supervisors during power on and off:
N VDD(INTREGD) using a fixed threshold
N VDD(INTF) using resistor bridge threshold adjustment
I Built-in debouncing on card presence contacts (typically 4.5 ms)
I Multiplexed status signal using pin OFFN
3. Applications
I Pay TV
I Electronic payment
I Identification
I Bank card readers
1 page  
NXP Semiconductors
7. Pinning information
www.datasheet4u.com
7.1 Pinning
TDA8025
IC card interface
terminal 1
index area
CMDVCCN
TEST1
TEST2
VDD(INTF)
CLKDIV2
CLKDIV1
VCC_SEL1
VCC_SEL2
1
2
3
4
5
6
7
8
TDA8025
24 TEST3
23 OFFN
22 RSTIN
21 VDDI(REG)
20 GND
19 VDD(INTREGD)
18 VCC
17 RST
Transparent top view
Fig 2. Pin configuration (HVQFN32)
001aai958
7.2 Pin description
Table 3. Pin description
Symbol
Pin Type[1] Description
CMDVCCN 1 I
microcontroller start activation sequence input; active LOW
TEST1
2I
test pin; connect to GND
TEST2
3I
test pin; connect to GND
VDD(INTF)
CLKDIV2
4P
5I
interface supply voltage
sets the clock frequency; used together with pin CLKDIV1;
see Table 4 on page 12
CLKDIV1 6 I
sets the clock frequency; used together pin CLKDIV2; see Table 4 on
page 12
VCC_SEL1 7 I
optional 1.2 V selection control signal:
active HIGH: VCC = 1.2 V
active LOW: disables 1.2 V selection
VCC_SEL2 8 I
3 V or 1.8 V selection control signal:
PRESN
9I
active LOW: VCC = 3 V
active HIGH: VCC = 1.8 V when pin VCC_SEL1 is active LOW
card presence contact input; active LOW[2]
PRES
10 I
card presence contact input; active HIGH[2]
I/O
11 I/O
card input/output data line (C7)[3]
AUX2
12 I/O
card auxiliary 2 input/output data line (C8)[3]
AUX1
13 I/O
card auxiliary 1 input/output data line (C4)[3]
TDA8025_1
Product data sheet
Rev. 01 — 6 April 2009
© NXP B.V. 2009. All rights reserved.
5 of 38
5 Page 
NXP Semiconductors
TDA8025
IC card interface
w
w
w
.
d
a
t
a
s
-R----1---n--o---m--
hR 2en o me
=
t
(-(--11--4--+-–----ββ-u---))
⋅
.
V-----D----D---(--I--N---T---F---)--a---c--t--m---i--n
c Vo thm(max)
–
1
R2nom = ---1-----+--R----RR--s----u--21---m---nn-----oo-----mm------- = ---1-----+-----(-(----11---------+-–--------β-β-------))----⋅------V-------R--D-----s---D--u--V--(-m---I--t--N--h-----(T---m--F------a-)----ax-----)c----t----m-------i---n----–-----1-------
(9)
(10)
If we target 1 % accuracy resistors (β = 0.01) and Rsum = 100 kΩ; Vth(max) = 1.33 V (see
Table 8 on page 23) and VDD(INTF)actmin = 2.64 V then
• R1nom = 50.88 kΩ
• R2nom = 49.12 kΩ
Deactivation always occurs when
V PORADJ < V th(min) ⇒ V DD(INTF)deactmax = V----α-t-h--m-(--m-a--xi--n---)
(11)
where
• Vth(min) is the minimum falling external threshold voltage
• VDD(INTF)deactmax is the maximum value of VDD(INTF) below which deactivation always
occurs
• αmax
αmax = 1-----+------RR--------21------nn-----o-o----m-1m---------⋅⋅------((-----11---------+–---------β-β-------))- = V-----D----D---(--VI--N--t-T-h--F(--m-)--d-i-n-e--)a---c--t--m---a---x
(12)
With the resulting values for R1nom, R2nom and β; Vth(min) = 1.17 V (see Table 8 on
page 23) then VDD(INTF)deactmax is 2.28 V.
8.3 Clock circuits
The clock signal (pin CLK) to the card is either generated by the clock signal input on pin
XTAL1 or from a crystal (fxtal ≤ 26 MHz) connected between pins XTAL1 and XTAL2. The
voltage level applied to pin ENCLKIN defines which clock signal is used. When pin
ENCLKIN is HIGH, connect the external clock to pin XTAL1.
Driving pin ENCLKIN LOW causes the external crystal to generate frequency fxtal. Using
pins CLKDIV1 and CLKDIV2, the crystal frequency can be set to either fxtal, 1⁄2 fxtal, 1⁄4 fxtal
or 1⁄8 fxtal.
The frequency change is synchronous and as such during transition, no pulse is shorter
than 45 % of the smallest period. In addition, only the first and last clock pulse around the
change have the correct width. When dynamically changing the frequency, the
modification is only effective after 10 periods of XTAL1.
TDA8025_1
Product data sheet
Rev. 01 — 6 April 2009
© NXP B.V. 2009. All rights reserved.
11 of 38
11 Page | ||
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