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PDF LE28F4001T Data sheet ( Hoja de datos )
| Número de pieza | LE28F4001T | |
| Descripción | 4 MEG (524288 words x 8 bits) Flash Memory | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LE28F4001T (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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Ordering number : EN*5239A
CMOS LSI
LE28F4001M, T, R-15/20
4 MEG (524288 words × 8 bits) Flash Memory
Preliminary
Overview
The LE28F4001 Series ICs are 524288-word × 8-bit flash
memory products that support on-board reprogramming
and feature 5 V single-voltage power supply operation.
CMOS peripheral circuits were adopted for high speed,
low power, and ease of use. These products support a
sector (256 bytes) erase function for fast data rewriting.
Features
• Fabricated in a highly reliable 2-layer polysilicon
CMOS flash EEPROM process.
• Read and write operation from a 5 V single-voltage
power supply
• Sector erase function: 256 bytes per sector
• Fast access time: 150/200 ns
• Low power
— Operating current (read): 25 mA (maximum)
— Standby current: 20 µA (maximum)
• Highly reliable read and write operations
— Sector write cycles: 104 cycles
— Data retention time: 10 years
• Address and data latches
• Self-timer erase and programming
• Byte programming time: 35 µs (maximum)
• Write complete detection: Toggle bit and data polling
• Hardware and software data protection
• Pin assignment conforms to the JEDEC byte-wide
EEPROM standard
• Packages
SOP 32-pin (525 mil) plastic package :LE28F4001M
TSOP 40-pin (10 × 14 mm) plastic package :LE28F4001T
TSOP 40-pin (10 × 14 mm) plastic package :LE28F4001R
Package Dimensions
unit: mm
3205-SOP32
[LE28F4001M]
unit: mm
3087A-TSOP40
[LE28F4001T, R]
SANYO: SOP32
SANYO: TSOP40 (TYPE-I)
These FLASH MEMORY products incorporate technology licensed Silicon Storage Technology, Inc.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
63096HA (OT) No. 5239-1/14
1 page  
LE28F4001M, T, R-15/20
1. Sector erase operation
The sector erase operation consists of a setup command and an execute command. The setup commands sets the
device to a state where all the bytes in the sector can be erased electrically. A single sector has 256 bytes. Since
almost all applications use erase operations that are not whole-chip erase operations but rather are single sector erase
operations, this sector erase function significantly increases the flexibility and ease of use of the LE28F4001 Series.
The setup command is executed by writing 20H to the command register.
An execute command (D0H) must be written to the command register to execute the sector erase operation. The
sector erase operation starts on the rising edge of the WE pulse and is automatically completed under internal timing
control. Figure 6 shows the timing waveforms for this operation.
This two stage sequence in which a setup command and a following execute command are required guarantees that
the memory at the sector specified by the address data will not be erased accidentally.
2. Sector erase flowchart
The quick and reliable erasure of up to 256 bytes of memory can be achieved by following the sector erase flowchart
shown in Figure 1. The whole operation consists of executing two commands. A sector erase operation completes in
a maximum of 4 ms. Although the erase operation can be completed by executing a reset operation, the sector may
not be completely erased if that reset is executed before the 4 ms time out period elapses. The erase command can be
re-executed as many times as required before the erase completes. Excessive erasure cannot cause problems with the
LE28F4001 Series products.
3. Byte programming operation
The byte programming operation is started by writing a setup command (10H) to the command register.
Once the setup command is executed, the execute command is started by the next WE pulse transition. Figure 7
shows the timing waveforms for this operation. The address and the data are latched internally on the falling edge
and rising edge of the WE pulse, respectively. The WE rising edge also corresponds to the start of the programming
operation. The programming operation is automatically completed under internal timing control. Figures 2 and 7
show the programming characteristics and waveforms.
As mentioned previously, this two stage sequence in which a setup command and a following execute operation are
required guarantees that the memory cells will not be programmed accidentally.
4. Byte programming flowchart
Figure 2 shows the device data programming operation. This is effected by following the byte programming
flowchart. The byte programming command sets up the byte to be written. The address is latched on the falling edge
of WE or CE, whichever is later. The data bus is latched on the rising edge of WE or CE, whichever is earlier, and
the programming operation starts at that point. The completion of the write operation can be detected using either the
toggle bit or by polling a Data pin.
5. Reset operation
The reset command is a procedure for safely terminating an erase or programming command sequence. Writing FFH
to the command register after issuing an erase or programming setup command will safely cancel that operation. The
contents of memory will not be changed. The device goes to read mode after executing a reset command. The reset
command cannot activate the software data protect function. Figure 8 shows the timing waveforms.
6. Read operation
A read operation is performed by setting CE and OE, and then WE, to read mode. Figure 3 shows the read mode
timing waveforms, and the read mode conditions are shown as “functional logic”. A read cycle from the host
searches for the memory array data. The device remains in the read state until another command is written to the
command register.
As a default, the device will be in read mode in the write protect state from the time power is first applied until a
command is written to the command register. The unprotect sequence must be executed to perform a write operation
(erase or programming).
The read operation is controlled by CE and OE, and both must be set to the logic low level to activate the read
function. When CE is at the logic high level, the chip is in the unselected state and only draws the standby current.
OE controls the output pins. The device output pins will be in the high-impedance state if either CE or OE is at the
logic high level.
No. 5239-5/14
5 Page 
LE28F4001M, T, R-15/20
Figure 3 Read Cycle
Figure 4 WE Control Write Cycle
Figure 5 CE Control Write Cycle
No. 5239-11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LE28F4001T.PDF ] | |
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