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PDF LE28F4001CTS-12 Data sheet ( Hoja de datos )

Número de pieza LE28F4001CTS-12
Descripción 4M-Bit (512k 8) Flash EEPROM
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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Preliminary Specifications
CMOS LSI
LE28F4001CTS-12
4M-Bit (512k × 8) Flash EEPROM
Features
CMOS Flash EEPROM Technology
Single 5-Volt Read and Write Operations
Sector Erase Capability: 256 Bytes per sector
Fast Access Time: 120 ns
Low Power Consumption
Active Current(Read): 25 mA (Max.)
Standby Current: 20 µA (Max.)
High Read/Write Reliability
Sector-write Endurance Cycles: 104
10 Years Data Retention
Latched Address and Data
Self-timed Erase and Programming
Byte Programming: 40µs (Max.)
End of Write Detection:Toggle Bit/ DATA Polling
Hardware/Software Data Protection
JEDEC Standard Byte-Wide EEPROM Pinouts
Packages Available
LE28F4001CTS: 32-pin TSOP Normal(8×14mm)
Product Description
The LE28F4001C is a 512K ×8 CMOS sector erase, byte
program EEPROM. The LE28F4001C is manufactured
using SANYO's proprietary, high performance CMOS Flash
EEPROM technology. Breakthroughs in EEPROM cell
design and process architecture attain better reliability and
manufacturability compared with conventional approaches.
The LE28F4001C erases and programs with a 5-volt only
power supply. LE28F4001C conforms to JEDEC standard
pinouts for byte wide memories and is compatible with
existing industry standard EPROM, flash EPROM and
EEPROM pinouts.
program or data memory. For all system applications, the
LE28F4001C significantly improves performance and
reliability, while lowering power consumption when
compared with floppy diskettes or EPROM approaches.
EEPROM technology makes possible convenient and
economical updating of codes and control programs on-line.
The LE28F4001C improves flexibility, while lowering the
cost, of program and configuration storage applications.
Figure 1 shows the pin assignments for the 32 lead
Plastic TSOP packages. Figure 2 shows the functional block
diagram of the LE28F4001C. Pin description and operation
modes can be found in Tables 1 through 3.
Featuring high performance programming, the
LE28F4001C typically byte programs in 30µs. The
LE28F4001C typically sector (256 bytes) erases in 2ms. Both
program and erase times can be optimized using interface
feature such as Toggle bit or DATA Polling to indicate the
completion of the write cycle. To protect against an
inadvertent write, the LE28F4001C has on chip hardware and
software date protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, the
LE28F4001C is offered with a guaranteed sector write
endurance of 104 cycles. Data retention is rated greater then
10 years.
The LE28F4001C is best suited for applications that
require reprogrammable nonvolatile mass storage of
Device Operation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the device
using standard microprocessor write sequences. A command
is written by asserting WE low while keeping CE low.
The address bus is latched on the falling edge of WE , CE ,
whichever occurs last. The data bus is latched on the rising
edge of WE , CE , whichever occurs first. However, during
the software write protection sequence the address are
latched on the rising edge of OE or CE , whichever occurs
first.
*This product incorporate technology licensed from Silicon Storage Technology, Inc.
This preliminary specification is subject to change without notice.
SANYO Electric Co., Ltd. Semiconductor Company
1-1, 1 Chome, Sakata, Oizumi-machi, Ora-gun, GUNMA, 370-0596 JAPAN
Revision 2.20-February 23,2001-AY/ay-1/14

1 page




LE28F4001CTS-12 pdf
Preliminary Specifications
LE28F4001CTS-12
4M-Bit Flash EEPROM
Read_ID Operation
DATA Polling (DQ7)
The Read_ID operation is initiated by writing a single
command (90H). A read of address 0000H will outputs the
manufacturer’s code (BFH). A read of address 0001H will outputs
the device code (04H).Any other valid command will terminate this
operation.
Data Protection from Inadvertent Writes
The LE28F4001C features DATA Polling to indicate the and
of a write cycle. During a write cycle, any attempt to read the last
byte loaded will result in the complement of the loaded data on
DQ7. Once the write cycle is completed, DQ7 will show true data.
See Figure 13 for timing waveforms. In order for DATA Polling
to function correctly, the byte being polled must be erased prior to
programming.
In order to protect the integrity of nonvolatile data storage, the
LE28F4001C provides hardware and software features to prevent
writes to the device, for example, during system power-up or
power-down. Such provisions are described below.
Hardware Write Protection
The LE28F4001C is designed with hardware features to
prevent inadvertent writes. This is done in the following ways:
1. Write Inhibit Mode: OE low, CE high or WE high
inhibit the write operation.
2. Noise and Glitch Protection: Write operations are initiated
when the WE pulse width is less than 15 ns.
3. After power-up the device is in the read mode and the
device is in the write protect state.
Software Data Protection
Provisions have been made to further prevent inadvertent writes
through software. In order to perform the write functions of erase
or program, a two-step command sequence consisting of a setup
command followed by an execute command avoids inadvertent
erasing or programming of the device.
The LE28F4001C will default to write protect after power-up.
A sequence of seven consecutive reads at specified device
addresses will unprotect the device. The address sequence is
1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 041AH. The
address has to be latched in the rising edge of OE or CE ,
whichever occurs first. A similar seven read sequence of 1823H,
1820H, 1822H, 0418H, 041BH, 0419H, 040AH will protect the
device. Also, refer to Figure 11, 12 for the 7-read-sequence
Software Write Protection. The DQ pins can be in any state (i.e.,
high, low, or High-Z).
Toggle Bit (DQ6)
An alternate means for determining the end of a write cycle is
by monitoring the Toggle Bit DQ6. During a write operation,
successive attempts to read data from the device will result in DQ6
toggling between logic "1" (high) and "0" (low). Once the write
cycle has completed, DQ6 will stop toggling and valid data will be
read. The Toggle Bit may be monitored any time during the write
cycle. See Figure 14 for timing waveforms.
Successive Reads
An alternate means for determining the end of a write cycle is
by reading the same address for two consecutive data matches.
Product Identification
The Product Identification mode identifies the device and
manufacturer as SANYO. This mode may be accessed by hardware
or software operations. The hardware operation is typically used by
an external programming to identify the correct algorithm for the
SANYO LE28F4001C. Users may wish to use the software
operation to identify the device (i.e., using the device code). For
details, see Table 2 for the hardware operation. The manufacturer
and device codes are the same for both operations.
Notes for Operation
During power up, the device’s state should be the write
inhibition mode. (During power up, the device’s state should be
CE =VIH or OE =VIL or WE =VIH)
If CE = WE =VIL and OE =VIH during power up, RESET
command should be asserted before operation.
End of Write Detection
Detection of where a write cycle ended is necessary to optimize
system performance. The end of a write cycle (erase or program)
can be detected by three means: 1) monitoring the DATA polling
bit; 2) monitoring the Toggle bit; 3) by two successive reads of the
same data. These three detection mechanisms are described below.
SANYO Electric Co., Ltd.
5/14

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LE28F4001CTS-12 arduino
Preliminary Specifications
LE28F4001CTS-12
4M-Bit Flash EEPROM
Figure 7: CE Controlled Write Cycle Timing Diagram
A18-0
CE
OE
WE
DQ7-0
tAS
tOES
tAH
tCP
tCPH
tOEH
tDS tDH
DATA VALID
Figure 8: Sector Erase Timing Diagram
A18-0
WE(CE)
OE
CE(WE)
DQ7-0
Setup command
tDS tDH
(20H)
Execute command
AIN
tAS
tAH
Self-timed Page
Erase Cycle
tSE
tDS tDH
(D0H)
SANYO Electric Co., Ltd.
11/14

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