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PDF LE28C1001T Data sheet ( Hoja de datos )

Número de pieza LE28C1001T
Descripción 1MEG (131072 words x 8 bits) Flash Memory
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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No Preview Available ! LE28C1001T Hoja de datos, Descripción, Manual

Ordering number : EN*5129A
CMOS LSI
LE28C1001M, T-90/12/15
Preliminary
1MEG (131072 words × 8 bits) Flash Memory
Overview
The LE28C1001M, T series ICs are 1 MEG flash memory
products that feature a 131072-word × 8-bit organization
and 5 V single-voltage power supply operation. CMOS
peripheral circuits are adopted for high speed, low power
dissipation, and ease of use. A 128-byte page rewrite
function provides rapid data rewriting.
Features
• Highly reliable 2-layer polysilicon CMOS flash
EEPROM process
• Read and write operations using a 5 V single-voltage
power supply
• Fast access time: 90, 120, and 150 ns
• Low power dissipation
— Operating current (read): 30 mA (maximum)
— Standby current:
20 µA (maximum)
• Highly reliable read/write
— Erase/write cycles:
104/103 cycles
— Data retention:
10 years
• Address and data latches
• Fast page rewrite operation
— 128 bytes per page
— Byte/page rewrite time: 5 ms (typical)
— Chip rewrite time:
5 s (typical)
• Automatic rewriting using internally generated Vpp
• Rewrite complete detection function
— Toggle bit
— Data polling
• Hardware and software data protection functions
• All inputs and outputs are TTL compatible.
• Pin assignment conforms to the JEDEC byte-wide
EEPROM standard.
• Package
SOP 32-pin (525 mil) plastic package : LE28C1001M
TSOP 32-pin (8 × 20 mm)plastic package : LE28C1001T
Package Dimensions
unit: mm
3205-SOP32
[LE28C1001M]
unit: mm
3224-TSOP32
[LE28C1001T]
SANYO: SOP32
SANYO: TSOP32 (TYPE-I)
These FLASH MEMORY products incorporate technology licensed Silicon Storage Technology, Inc.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
D3096HA (OT)/N3095HA (OT) No. 5129-1/14

1 page




LE28C1001T pdf
LE28C1001M, T-90/12/15
Data Protection
Hardware Data Protection
Noise and glitch protection: The LE28C1001M, T series do not execute write operations for WE or OE pulses that are 15
ns or shorter.
Power (VCC) on and cutoff detection: The programming operation is disabled when VCC is 2.5 V or lower.
Write inhibit mode: Writing is disabled when OE is low and either CE is high or WE is high. Use this function to prevent
writes from occurring when the power is being turned on or off.
Software Data Protection
The LE28C1001M, T series implement the optional software data protection function recognized by JEDEC. This
function requires a 3-byte load operation to be performed before a write operation data load. The 3-byte load sequence
starts a page load cycle without activating any write operation. Thus this is an optimal protection scheme for unintended
write cycles triggered by noise associated with powering the chip on or off. Note that the LE28C1001M, T series are
shipped with the software data protection function disabled.
The software data protection circuit is activated by executing a 3-byte byte load cycle in advance of the data sequence in
the page load cycle. (See Figure 6.) This causes the device to automatically enter data protection mode. After this, write
operations require a 3-byte byte load cycle to be executed in advance. A 6-byte write sequence is required to switch the
device out of this protection mode. Figure 7 shows the timing diagram. If a write operation is attempted in software
protection mode, all device functions are disabled for 200 µs. Figure 12 shows the flowchart for this operation.
Chip Erase
The LE28C1001M, T series provide a chip erase mode that erases all of the memory cell array and sets each bit to the 1
state. This mode can be effective when it is necessary to erase all data quickly.
5 V Single-Voltage Power Supply Software Chip Erase
The software chip erase mode operation is started by executing a specially defined 6-byte byte load sequence, similar to
page mode operation under software protection. After the load cycle is executed, the device enters an internal
programming cycle similar to the write cycle. Figure 8 shows the timing diagram and Figure 14 shows the flowchart for
this operation.
Product Identification
The device identification code is used for recognizing the device and its manufacturer. This mode can be used by
hardware and software. The hardware operating mode is used to recognize algorithms that match the device when an
external programming unit is used. Also, user systems can recognize the product number using software product
identification mode. Figure 13 shows the flowchart for this operation. The manufacturer and device codes are the same
in both modes.
No. 5129-5/14

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LE28C1001T arduino
LE28C1001M, T-90/12/15
Figure 10 Write Algorithm
No. 5129-11/14

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