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PDF CH5001A Data sheet ( Hoja de datos )
| Número de pieza | CH5001A | |
| Descripción | CMOS COLOR DIGITAL VIDEO CAMERA | |
| Fabricantes | Chrontel | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CH5001A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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CH5001A
CHRONTEL
CMOS Color Digital Video Camera
www.daFtaeshaeettu4ur.ceoms
• 352 x 288 active pixel array with color filters, 1/3 inch
lens format ¥
• Programmable formats CIF 352x288, QCIF 176x144,
CCIR601 704x288
• Digital output CCIR601 4:2:2 (8-bit or 16-bit)
• Multidimensional automatic shutter control
• Below 5 LUX sensitivity
• Programmable I2C Serial bus control:
- Frame rate: 30fps-1fps in eight steps
- Gamma correction
- Shutterspeed
- Analog gain
- 16 backlight compensation zones
- Black clamp level
- White balance adjustment
- Power down modes
• Stand-alone 25fps PAL operation with all automatic
features
• Single crystal operation: Video timing on-chip
• Single 5V power supply
• Less than 0.5 watt power dissipation
¥ Patent number x,xxx,xxx patents pending
Description
The CH5001 is a single chip active pixel CMOS color
video camera with digital video output in several formats.
Using sophisticated noise correction circuitry to minimize
fixed pattern noise and dark current effects, the CH5001
provides a supurb quality picture in a low cost device.
The CH5001 uses a proprietary autoshutter algorithm to
dynamically control the shutter time, analog gain, and
black clamp level, providing optimum picture and contrast
under all lighting conditions. The CH5001 also
incorporates extensive on-chip programmable digital
signal processing to maximize the usefulness of the device
in processor driven applications. This includes 16
programmable zones for backlight compensation,
allowing the user to adjust the image to their unique
lighting environment.
Additionally, at power-up the backlight compensation
zone, power-up condition, and direct A/D output modes
are selectable without IIC control by using the PUD pins.
Requiring a minimum of parts for operation, the CH5001
provides a low cost camera for the next generation video
conferencing, videophone, and surveillance products.
Photocell
352
Columns
Array
BG
GR
288
Rows
Row Decode
R
O Shutter
W Control
T
I
M
I
N
G
Color
Control
Gain
A/D
Black
Clamp
Matrix Gamma
Multiply Correct
RGB
to
YCrCB
Filter
Figure 1: Block Diagram
I 2C
BUS
Timing
&
Mode
Control
Output
Format
SD
SC
AS
HREF
PDP*
HS*
VS*
CLKOUT
Reset*
XI/Fin
XO
MONO
TOUT/TOUTB
OVR
Y[7:0]
C[7:0] PUD[6:0]
CRS
201-0000-032 Rev 3.0, 6/2/99
1
3
1 page  
CHRONTEL
Table 1. Pin Descriptions
Pin
40, 46, 51
Type
Power
Symbol
AVDD
41
www.datasheet4u.com
Out VREF
37, 43, 48
Power
AGND
42 Out CRF
49, 50
44, 45
In/Out
Out
TOUT, TOUTB
ARF2, ARF
47 Out VRS
1 In MONO
35 In
PDP*
52 Out CMB2
31-25
In
PUD[5:0]*
PUD[6]
CH5001A
Description
Analog Supply Voltage
Supplies the 5V power to the analog section of the CH5001.
Voltage Reference
VREF provides a 1.235V reference. A 0.01µF decoupling capacitor
should be connected between VREF and AGND.
Analog Ground
These pins provide the ground reference for the analog section of
CH5001. Pins must be connected to the system ground to prevent
latchup.
Column Filter
CRF provides a 2.5 V reference. A 0.1µF decoupling capacitor should
be connected between CRF and AGND.
Test Mode I/O Pins
For test purposes only. Should be NC.
Array Filters
A 0.1uF decoupling capacitors should be connected between each of
the pins and AGND.
Array Bias Filter
VRS provides a 2.1V reference. A 0.1µF decoupling capacitor should
be connected between VRS and AGND.
Monochrome (active high, internal pulldown)
Digital pin to select Color / Monochrome operation.
1= Monochrome 0=Color
Power Down Pin (active low, internal pullup)
0 = power down
Bias Filter
A 0.1µF decoupling capacitor should be connected between CMB2 and
AGND.
Power Up Detect (internal pull-up)
These pins are shared with the C[6:0] chrominance output function. At
power-up they are inputs controlling the default value of IIC register bits
M0, ADDO, PD, ASW[3:0]. Attach 100K Ohms to DGND to pull low.
NOTE: PUD[5:0]* are logically inverted
201-0000-032 Rev 3.0, 6/2/99
5
5 Page 
CHRONTEL
CH5001A
Due to the desired noise margin of 0.2VDD for the HIGH level, this input current limits the maximum value of RP.
The RP limit depends on VDD and is shown below:
RP >= (100 x VDD)/ Iinput (where: RP is in kΩ and Iinput is in µA) Transfer Protocol
Both read and write cycles can be executed in Alternating and Auto-increment modes. Alternating mode expects a
www.datashreeegt4iust.ceormaddress prior to each read or write from that location (i.e., transfers alternate between address and data).
Auto-increment mode allows you to establish the initial register location, then automatically increments the register
address after each subsequent data access (i.e., transfers will be address, data, data, data...). A basic serial port
transfer protocol is shown in Figure 5 and described below.
SD
SC 1 - 7 8 9 1 - 8 9
Start
Condition
Device ID
R/W* ACK
CH5001
acknowledge
Data1
ACK
CH5001
acknowledge
1-8 9
Data n
ACK
CH5001
acknowledge
Stop
Condition
Figure 5: Serial Port Transfer Protocol
1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the
START condition. Transitions of address and data bits can only occur while SC is low.
2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the
STOP condition.
3. Upon receiving the first START condition, the CH5001 expects a Device Address Byte (DAB) from the
master device. The value of the device address is shown in the DAB data format below. Note that B[2:1] is
determined by the state of the AS pin (see Table 1 for details).
Table 3. Device Address Byte (DAB)
B7 B6 B5 B4 B3 B2 B1 B0
1 0 0 0 1 AS* AS R/W
4. After the DAB is received, the CH5001 expects a Register Address Byte (RAB) from the master. The
format of the RAB is shown in the RAB data format below (note that B7 is not used).
R/W Read/Write Indicator
0: Master device will write to the CH5001 at the register location specified by the address
AR[5:0]
1: Master device will read from the CH5001 at the register location specified by the
address AR[5:0]. AutoInc Register Address Auto-Increment - to facilitate sequential
R/W of registers 1: Auto-Increment enabled (auto-increment mode).
201-0000-032 Rev 3.0, 6/2/99
11
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