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PDF CDK8307 Data sheet ( Hoja de datos )

Número de pieza CDK8307
Descripción Ultra Low Power ADC
Fabricantes Cadeka 
Logotipo Cadeka Logotipo



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No Preview Available ! CDK8307 Hoja de datos, Descripción, Manual

PRELIMINARY Data Sheet
Amplify the Human Experience
CDK8307
12/13-bit, 20/40/50/65MSPS, Eight Channel,
Ultra Lowwww.datasheet4u.com Power ADC with LVDS
FEATURES
n 20/40/50/65MSPS maximum sampling rate
n Low Power Dissipation
– 22mW/channel at 20MSPS
– 34mW/channel at 40MSPS
– 40mW/channel at 50MSPS
– 50mW/channel at 65MSPS
n 72.2dB SNR at 8MHz FIN
n 0.5μs startup time from Sleep
n 15μs startup time from Power Down
n Internal reference circuitry requires no
external components
n Internal offset correction
n Reduced power dissipation modes available
– 32mW/channel at 50MSPS
– 71.5dB SNR at 8MHz FIN
n Coarse and fine gain control
n 1.8V supply voltage
n Serial LVDS output
– 12- and 14-bit output available
n Package alternatives
– TQFP-80
– QFN-64
APPLICATIONS
n Medical Imaging
n Wireless Infrastructure
n Test and Measurement
n Instrumentation
General Description
The CDK8307 is a high performance low power octal analog-to-digital
converter (ADC). The ADC employs internal reference circuitry, a serial control
interface and serial LVDS output data, and is based on a proprietary structure.
An integrated PLL multiplies the input sampling clock by a factor of 12 or 14,
according to the LVDS output setting. The multiplied clock is used for data
serialization and data output. Data and frame synchronization output clocks are
supplied for data capture at the receiver.
Various modes and configuration settings can be applied to the ADC through
the serial control interface (SPI). Each channel can be powered down inde-
pendently and data format can be selected through this interface. A full chip
idle mode can be set by a single external pin. Register settings determines the
exact function of this external pin.
The CDK8307 is designed to easily interface with field-programmable gate
arrays (FPGAs) from several vendors.
The very low startup times of the CDK8307 allow significant power reduction
in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when
the receive path is idle.
Block Diagram
Serial Control
Interface
IP1
IN1
ADC
IP2
IN2
ADC
•••
IP8
IN8
ADC
Clock
Input
PLL
LVDS
Digital
Gain
LVDS
Digital
Gain
•••
Digital
Gain
LVDS
•••
LVDS
FCLKP
FCLKN
LCLKP
LCLKN
D1N
D1P
D2N
D2P
D8N
D8P
©2009 CADEKA Microcircuits LLC
www.cadeka.com

1 page




CDK8307 pdf
PRELIMINARY Data Sheet
Pin Assignments
Pin No.
QFN-64
49, 50, 57
www.data3s,he6e, t94u, .3c7o,m40, 43, 46, 52
1
2
4
5
7
8
10
11
38
39
41
42
44
45
47
48
12, 14, 36
35
13
15
16
17
18
19
20
21
22
27
28
29
30
31
32
33
34
23
24
25
26
©2009 CADEKA Microcircuits LLC
Pin Name Description
AVDD
AVSS
IP1
IN1
IP2
IN2
IP3
IN3
IP4
IN4
IP5
IN5
IP6
IN6
IP7
IN7
IP8
IN8
DVSS
DVDD
PD
D1P
D1N
D2P
D2N
D3P
D3N
D4P
D4N
D5P
D5N
D6P
D6N
D7P
D7N
D8P
D8N
FCLKP
FCLKN
LCLKP
LCLKN
Analog power supply, 1.8V
Analog ground
Positive differential input signal, channel 1
Negative differential input signal, channel 1
Positive differential input signal, channel 2
Negative differential input signal, channel 2
Positive differential input signal, channel 3
Negative differential input signal, channel 3
Positive differential input signal, channel 4
Negative differential input signal, channel 4
Positive differential input signal, channel 5
Negative differential input signal, channel 5
Positive differential input signal, channel 6
Negative differential input signal, channel 6
Positive differential input signal, channel 7
Negative differential input signal, channel 7
Positive differential input signal, channel 8
Negative differential input signal, channel 8
Digital ground
Digital and I/O power supply, 1.8V
Power-down input
LVDS channel 1, positive output
LVDS channel 1, negative output
LVDS channel 2, positive output
LVDS channel 2, negative output
LVDS channel 3, positive output
LVDS channel 3, negative output
LVDS channel 4, positive output
LVDS channel 4, negative output
LVDS channel 5, positive output
LVDS channel 5, negative output
LVDS channel 6, positive output
LVDS channel 6, negative output
LVDS channel 7, positive output
LVDS channel 7, negative output
LVDS channel 8, positive output
LVDS channel 8, negative output
LVDS frame clock (1x), positive output
LVDS frame clock (1x), negative output
LVDS bit clock, positive output
LVDS bit clock, negative output
www.cadeka.com 5

5 Page





CDK8307 arduino
PRELIMINARY Data Sheet
Electrical Characteristics - CDK8307B
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted)
Symbol Parameter
Performance
SNR Signal to Noise Ratio
wwwS.IdNaAtaDsheet4u.Sciogmnal to Noise and Distortion Ratio
SFDR
Spurious Free Dynamic Range
HD2 Second order Harmonic Distortion
HD3 Third order Harmonic Distortion
ENOB
Effective number of Bits
Crosstalk
Power Supply
Clock Inputs
Analog supply current
Digital supply current
Analog power Dissipation
Digital power Dissipation
Total power Dissipation
Power Down Dissipation
Sleep Mode Dissipation
Sleep Channel Mode Dissipation
Sleep Channel Mode Savings
Maximum Conversion Rate
Minimum Conversion Rate
Conditions
Min Typ Max Units
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
Signal applied to 7 channels (FIN0).
Measurement taken on one channel with full
scale at FIN1. FIN1 = 8MHz, FIN0 = 9.9MHz
72.2
71.5
82
95
82
11.6
95
dBFS
dBFS
dBc
dBc
dBc
bits
dBc
91 mA
Digital and output driver supply
60 mA
164 mW
108 mW
272 mW
10 µW
67 mW
Power dissipation with all chs in sleep mode 72 mW
Power dissipation savings per channel off
23 mW
40 MSPS
20 MSPS
Electrical Characteristics - CDK8307C
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted)
Symbol Parameter
Performance
SNR Signal to Noise Ratio
SINAD
Signal to Noise and Distortion Ratio
SFDR
Spurious Free Dynamic Range
HD2 Second order Harmonic Distortion
HD3 Third order Harmonic Distortion
ENOB
Effective number of Bits
Crosstalk
Power Supply
Analog supply current
Digital supply current
Analog power Dissipation
Digital power Dissipation
Total power Dissipation
Power Down Dissipation
Sleep Mode Dissipation
Conditions
Min Typ Max Units
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
Signal applied to 7 channels (FIN0).
Measurement taken on one channel with full
scale at FIN1. FIN1 = 8MHz, FIN0 = 9.9MHz
Digital and output driver supply
72.2
71.5
82
95
82
11.6
95
112
66
202
119
321
10
78
dBFS
dBFS
dBc
dBc
dBc
bits
dBc
mA
mA
mW
mW
mW
µW
mW
©2009 CADEKA Microcircuits LLC
www.cadeka.com 11

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