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PDF CDK2308 Data sheet ( Hoja de datos )

Número de pieza CDK2308
Descripción 10-bit Analog-to-Digital Converters
Fabricantes Cadeka 
Logotipo Cadeka Logotipo



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No Preview Available ! CDK2308 Hoja de datos, Descripción, Manual

PRELIMINARY Data Sheet
CDK2308
Dual, 20/40/65/80MSPS, 10-bit
wwAw.ndaataslhoeegt4u-.ctoom -Digital Converters
Amplify the Human Experience
f ea t u re s
n 10-bit resolution
n 20/40/65/80MSPS maximum sampling rate
n Ultra-low power dissipation: 24/43/65/78mW
n 61.6dB SNR at 8MHz FIN
n Internal reference circuitry
n 1.8V core supply voltage
n 1.7V – 3.6V I/O supply voltage
n Parallel CMOS output
n 64-pin TQFP package
n Dual channel
n Pin compatible with CDK2307
A ppli c a t i o n s
n Medical Imaging
n Portable Test Equipment
n Digital Oscilloscopes
n IF Communication
General Description
The CDK2308 is a high performance, low power dual Analog-to-Digital Con-
verters (ADC). The ADC employs internal reference circuitry, a CMOS control
interface and CMOS output data, and is based on a proprietary structure.
Digital error correction is employed to ensure no missing codes in the com-
plete full scale range.
Several idle modes with fast startup times exist. Each channel can indepen-
dently be powered down and the entire chip can either be put in Standby
Mode or Power Down mode. The different modes are optimized to allow the
user to select the mode resulting in the smallest possible energy consumption
during idle mode and startup.
The CDK2308 has a highly linear THA optimized for frequencies up to Nyquist.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave and CMOS clock inputs.
Functional Block Diagram
CLK_EXT
Ordering Information
Part Number
CDK2308AITQ64
CDK2308AITQ64X
CDK2308BITQ64
CDK2308BITQ64X
CDK2308CITQ64
CDK2308CITQ64X
CDK2308DITQ64
CDK2308DITQ64X
Speed
20MSPS
20MSPS
40MSPS
40MSPS
65MSPS
65MSPS
80MSPS
80MSPS
Package
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
Moisture sensitivity level for all parts is MSL-3.
©2008 CADEKA Microcircuits LLC
Pb-Free
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RoHS Compliant
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Operating Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Packaging Method
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
www.cadeka.com

1 page




CDK2308 pdf
PRELIMINARY Data Sheet
Electrical Characteristics
(AVDD=1.8V, DVDD=1.8V, DVDDCLK=1.8V, OVDD=2.5V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal,
13-bit output, unless otherwise noted)
Symbol Parameter
DC Accuracy
www.datasheet4u.NcoomMissing Codes
Offset Error
Gain Error
Gain Matching
DLE Differential Non-Linearity
ILE Integral Non-Linearity
VCMO
Common Mode Voltage Output
Analog Input
VCMI Input Common Mode
Full Scale Range, Normal
VFSR Full Scale Range, Option
Power Supply
Input Capacitance
Bandwidth
AVDD, DVDD Core Supply Voltage
OVDD
I/O Supply Voltage
Conditions
Min Typ Max Units
Midscale offset
Full scale range deviation from typical
Gain matching between channels
12-bit level
12-bit level
Analog input common mode voltage
Differential input voltage range,
Differential input voltage range, 1V
(see section Reference Voltages)
Differential input capacitance
Input bandwidth, full power
Guaranteed
TBD
-6 6
±0.05
-1 1
-1 1
VAVDD/2
mV
%FS
%FS
LSB
LSB
V
VCM -0.1
VCM +0.1
V
2.0 Vpp
1.0 Vpp
1.8
500
pF
MHz
Supply voltage to all 1.8V domain pins.
See Pin Configuration and Description
1.7 1.8 1.9
Output driver supply voltage (OVDD).
1.7 2.5 3.6
Must be higher than or equal to Core Supply
Voltage (VOVDD ≥ VOCVDD)
V
V
©2008 CADEKA Microcircuits LLC
www.cadeka.com 5

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CDK2308 arduino
PRELIMINARY Data Sheet
www.datasheet4u.com
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+F2
+F
+ +F0
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N-12
N-11
N-10
N-9
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CLK_EXT
Figure 1. Timing Diagram
Recommended Usage
Analog Input
The analog inputs to the CDK2308 is a switched capacitor
track-and-hold amplifier optimized for differential opera-
tion. Operation at common mode voltages at mid sup-
ply is recommended even if performance will be good for
the ranges specified. The CM_EXT pin provides a voltage
suitable as common mode voltage reference. The internal
buffer for the CM_EXT voltage can be switched off, and
driving capabilities can be changed by using the CM_EXT-
BC control input.
Figure 2 shows a simplified drawing of the input network.
The signal source must have sufficiently low output imped-
ance to charge the sampling capacitors within one clock
cycle. A small external resistor (e.g. 22Ω) in series with
each input is recommended as it helps reducing transient
currents and dampens ringing behavior. A small differential
shunt capacitor at the chip side of the resistors may be
used to provide dynamic charging currents and may im-
prove performance. The resistors form a low pass filter
with the capacitor, and values must therefore be deter-
mined by requirements for the application.
DC-Coupling
Figure 3 shows a recommended configuration for DC-
coupling. Note that the common mode input voltage must
be controlled according to specified values. Preferably, the
CM_EXT output should be used as a reference to set the
common mode voltage.
The input amplifier could be inside a companion chip or
it could be a dedicated amplifier. Several suitable single
ended to differential driver amplifiers exist in the market.
The system designer should make sure the specifications
of the selected amplifier is adequate for the total system,
and that driving capabilities comply with the CDK2308
input specifications.
Ω
pF
Ω
Figure 3. DC-Coupled Input
Detailed configuration and usage instructions must be
found in the documentation of the selected driver.
Figure 2. Input Configuration
AC-Coupling
A signal transformer or series capacitors can be used to
make an AC-coupled input network. Figure 4 shows a
recommended configuration using a transformer. Make
sure that a transformer with sufficient linearity is selected,
©2008 CADEKA Microcircuits LLC
www.cadeka.com 11

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