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PDF CDK2307 Data sheet ( Hoja de datos )
| Número de pieza | CDK2307 | |
| Descripción | 12/13-bit Analog-to-Digital Converters | |
| Fabricantes | Cadeka | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CDK2307 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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Data Sheet
CDK2307
Dual, 20/40/65/80MSPS, 12/13-bit
wwAw.ndaataslhoeegt4u-.ctoom -Digital Converters
Amplify the Human Experience
FEATURES
n 13-bit resolution
n 20/40/65/80MSPS maximum sampling rate
n Ultra-low power dissipation: 30/55/85/102mW
n SNR 72dB at 80MSPS and 8MHz FIN
n Internal reference circuitry
n 1.8V core supply voltage
n 1.7V – 3.6V I/O supply voltage
n Parallel CMOS output
n 64-pin QFN package
(TQFP-64 package option also available)
n Dual channel
n Pin compatible with CDK2308
APPLICATIONS
n Handheld Communication, PMR, SDR
n Medical Imaging
n Portable Test Equipment
n Digital Oscilloscopes
n Baseband / IF Communication
n Video Digitizing
n CCD Digitizing
General Description
The CDK2307 is a high performance, low power dual Analog-to-Digital Con-
verter (ADC). The ADC employs internal reference circuitry, a CMOS control
interface and CMOS output data, and is based on a proprietary structure.
Digital error correction is employed to ensure no missing codes in the com-
plete full scale range.
Several idle modes with fast startup times exist. Each channel can be inde-
pendently powered down and the entire chip can either be put in Standby
Mode or Power Down mode. The different modes are optimized to allow the
user to select the mode resulting in the smallest possible energy consumption
during idle mode and startup.
The CDK2307 has a highly linear THA optimized for frequencies up to 70MHz.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave and CMOS clock inputs.
Functional Block Diagram
CLK_EXT
Ordering Information (QFN-6 Package)
Part Number
Speed Package
CDK2307AILP64
CDK2307AILP64X
20MSPS QFN-64
20MSPS QFN-64
CDK2307BILP64
CDK2307BILP64X
40MSPS QFN-64
40MSPS QFN-64
CDK2307CILP64
CDK2307CILP64X
CDK2307DILP64
CDK2307DILP64X
65MSPS
65MSPS
80MSPS
80MSPS
QFN-64
QFN-64
QFN-64
QFN-64
Moisture sensitivity level for all parts is MSL-2A.
Pb-Free
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RoHS Compliant
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Operating Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Packaging Method
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
©2009 CADEKA Microcircuits LLC
www.cadeka.com
1 page  
Data Sheet
Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol Parameter
DC Accuracy
www.datasheet4u.NcoomMissing Codes
Offset Error
Gain Error
Gain Matching
DNL
INL
VCMO
Analog Input
VCMI
VFSR
Differential Non-Linearity
Integral Non-Linearity
Common Mode Voltage Output
Input Common Mode
Full Scale Range, Normal
Full Scale Range, Option
Power Supply
Input Capacitance
Bandwidth
AVDD, DVDD Core Supply Voltage
OVDD
I/O Supply Voltage
Conditions
Min Typ Max Units
Midscale offset
Full scale range deviation from typical
Gain matching between channels. ±3 sigma
value at worst case conditions.
12-bit level
12-bit level
Guaranteed
1
-6 6
±0.5
±0.2
±0.6
VAVDD/2
LSB
%FS
%FS
LSB
LSB
V
Analog input common mode voltage
Differential input voltage range,
Differential input voltage range, 1V
(see section Reference Voltages)
Differential input capacitance
Input bandwidth, full power
VCM -0.1
VCM +0.2
V
2.0 Vpp
1.0 Vpp
2.0
500
pF
MHz
Supply voltage to all 1.8V domain pins.
See Pin Configuration and Description
1.7 1.8 2.0
Output driver supply voltage (OVDD).
1.7 2.5 3.6
Must be higher than or equal to Core Supply
Voltage (VOVDD ≥ VDVDD)
V
V
©2009 CADEKA Microcircuits LLC
www.cadeka.com 5
5 Page 
Data Sheet
www.datasheet4u.com
+F1 +F4
+F2
+F
+ +F0
N-13
CLK_EXT
Figure 1. Timing Diagram
Recommended Usage
Analog Input
The analog input to the CDK2307 is done through a
switched capacitor track-and-hold amplifier optimized for
differential operation. Operation at mid supply common
mode voltage is recommended even if performance will
be good for the ranges specified. The CM_EXT pin pro-
vides a voltage suitable for a common mode voltage refer-
ence. The internal buffer for the CM_EXT voltage can be
switched off, and driving capabilities can be changed by
using the CM_EXTBC control input.
Figure 2 shows a simplified drawing of the input network.
The signal source must have sufficiently low output imped-
ance to charge the sampling capacitors within one clock
cycle. A small external resistor (e.g. 22Ω) in series with
each input is recommended as it helps reducing transient
currents and dampens ringing behavior. A small differential
shunt capacitor at the chip side of the resistors may be
used to provide dynamic charging currents and may im-
prove performance. The resistors form a low pass filter
with the capacitor, and values must therefore be deter-
mined by requirements for the application.
DC-Coupling
Figure 3 shows a recommended configuration for DC-
coupling. Note that the common mode input voltage must
be controlled according to specified values. Preferably, the
CM_EXT output should be used as a reference to set the
common mode voltage.
The input amplifier could be inside a companion chip or
it could be a dedicated amplifier. Several suitable single
ended to differential driver amplifiers exist in the market.
The system designer should make sure the specifications
of the selected amplifier is adequate for the total system,
and that driving capabilities comply with the CDK2307
input specifications.
Ω
pF
Ω
Figure 3. DC-Coupled Input
Detailed configuration and usage instructions must be
found in the documentation of the selected driver.
Figure 2. Input Configuration
AC-Coupling
A signal transformer or series capacitors can be used to
make an AC-coupled input network. Figure 4 shows a
recommended configuration using a transformer. Make
sure that a transformer with sufficient linearity is selected,
©2009 CADEKA Microcircuits LLC
www.cadeka.com 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CDK2307.PDF ] | |
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