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PDF CDK1307 Data sheet ( Hoja de datos )
| Número de pieza | CDK1307 | |
| Descripción | 12/13-bit Analog-to-Digital Converters | |
| Fabricantes | Cadeka | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CDK1307 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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ADVANCE Data Sheet
Amplify the Human Experience
CDK1307
Ultra Low Power, 20/40/65/80MSPS,
12/13-bitwww.datasheet4u.com Analog-to-Digital Converters (ADCs)
FEATURES
n 13-bit resolution
n 20/40/65/80MSPS max sampling rate
n Ultra-Low Power Dissipation:
19/33/50/60mW
n 72.4dB SNR at 8MHz FIN
n Internal reference circuitry
n 1.8V core supply voltage
n 1.7 – 3.6V I/O supply voltage
n Parallel CMOS output
n 40-pin QFN package
n Pin compatible with CDK1308
APPLICATIONS
n Medical Imaging
n Portable Test Equipment
n Digital Oscilloscopes
n IF Communication
General Description
The CDK1307 is a high performance ultra low power Analog-to-Digital
Converter (ADC). The ADC employs internal reference circuitry, a CMOS
control interface and CMOS output data, and is based on a proprietary struc-
ture. Digital error correction is employed to ensure no missing codes in the
complete full scale range.
Two idle modes with fast startup times exist. The entire chip can either be
put in Standby Mode or Power Down mode. The two modes are optimized to
allow the user to select the mode resulting in the smallest possible energy
consumption during idle mode and startup.
The CDK1307 has a highly linear THA optimized for frequencies up to Nyquist.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave, and CMOS clock inputs.
Functional Block Diagram
Ordering Information
Part Number
CDK1307AILP40
CDK1307BILP40
CDK1307CILP40
CDK1307DILP40
Speed
20MSPS
40MSPS
65MSPS
80MSPS
Package
QFN-40
QFN-40
QFN-40
QFN-40
Moisture sensitivity level for all parts is MSL-3.
Pb-Free
Yes
Yes
Yes
Yes
RoHS Compliant
Yes
Yes
Yes
Yes
Operating Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Packaging Method
Tray
Tray
Tray
Tray
©2008 CADEKA Microcircuits LLC
www.cadeka.com
1 page  
ADVANCE Data Sheet
Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol Parameter
DC Accuracy
www.datasheet4u.NcoomMissing Codes
Offset Error
Gain Error
DNL Differential Non-Linearity
INL Integral Non-Linearity
VCMO
Common Mode Voltage Output
Analog Input
VCMI Input Common Mode
Full Scale Range, Normal
VFSR Full Scale Range, Option
Power Supply
AVDD,
DVDD
Input Capacitance
Bandwidth
Core Supply Voltage
OVDD
I/O Supply Voltage
Conditions
Min Typ Max Units
Midscale offset
Full scale range deviation from typical
12-bit level
12-bit level
Analog input common mode voltage
Differential input voltage range,
Differential input voltage range, 1V
(see section Reference Voltages)
Differential input capacitance
Input bandwidth, full power
Guaranteed
TBD
-6 6
-0.5 0.5
-1 1
VAVDD/2
mV
%FS
LSB
LSB
V
VCM -0.1
VCM +0.1
V
2.0 Vpp
1.0 Vpp
1.8
500
pF
MHz
Supply voltage to all 1.8V domain pins.
See Pin Configuration and Description
1.7 1.8 2.0
Output driver supply voltage (OVDD).
1.7 2.5 3.6
Must be higher than or equal to Core Supply
Voltage (VOVDD ≥ VOCVDD)
V
V
©2008 CADEKA Microcircuits LLC
www.cadeka.com 5
5 Page 
ADVANCE Data Sheet
www.datasheet4u.com
N+3 N+4
N+5
N+2
N N+1
N-13
CLK_EXT
Figure 1. Timing Diagram
Recommended Usage
Analog Input
The analog inputs to the CDK1307 is a switched capacitor
track-and-hold amplifier optimized for differential opera-
tion. Operation at common mode voltages at mid supply
is recommended even if performance will be good for the
ranges specified. The CM_EXT pin provides a voltage suit-
able as common mode voltage reference. The internal
buffer for the CM_EXT voltage can be switched off, and
driving capabilities can be changed by using the CM_EXT-
BC control input.
Figure 2 shows a simplified drawing of the input net-
work. The signal source must have sufficiently low output
impedance to charge the sampling capacitors within one
clock cycle. A small external resistor (e.g. 22Ω) in series
with each input is recommended as it helps reducing
transient currents and dampens ringing behavior. A small
differential shunt capacitor at the chip side of the resistors
may be used to provide dynamic charging currents and
may improve performance. The resistors form a low pass
filter with the capacitor, and values must therefore be
determined by requirements for the application.
DC-Coupling
Figure 3 shows a recommended configuration for DC-
coupling. Note that the common mode input voltage must
be controlled according to specified values. Preferably, the
CM_EXT output should be used as a reference to set the
common mode voltage.
The input amplifier could be inside a companion chip or
it could be a dedicated amplifier. Several suitable single
ended to differential driver amplifiers exist in the market.
The system designer should make sure the specifications
of the selected amplifier is adequate for the total system,
and that driving capabilities comply with the CDK1307 in-
put specifications.
Ω
pF
Ω
Figure 3. DC-Coupled Input
Detailed configuration and usage instructions must be
found in the documentation of the selected driver, and
the values given in Figure 3 must be varied according to
the recommendations for the driver.
Figure 2. Input Configuration
AC-Coupling
A signal transformer or series capacitors can be used
to make an AC-coupled input network. Figure 4 shows
©2008 CADEKA Microcircuits LLC
www.cadeka.com 11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CDK1307.PDF ] | |
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