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PDF IDT79R4700 Data sheet ( Hoja de datos )
| Número de pieza | IDT79R4700 | |
| Descripción | 64-Bit RISC Microprocessor | |
| Fabricantes | IDT | |
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64-Bit RISC Microprocessor
IDT79R4700
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x True 64-bit microprocessor
– 64-bit integer operations
– 64-bit floating-point operations
– 64-bit registers
– 64-bit virtual address space
x High-performance microprocessor
– 260 Dhrystone MIPS at 200MHz
– 100 peak MFLOP/s at 200MHz
– Two-way set associative caches
– Simple 5-stage pipeline
x High level of integration
– 64-bit, 200 MHz integer CPU
– 64-bit floating-point unit
– 16KB instruction cache
– 16KB data cache
– Flexible MMU with large, fully associative TLB
x Low-power operation
– 3.3V power supply, for the “RV” part
– 5V power supply, for the “R” part
– Dynamic power management
– Standby mode reduces internal power
x Fully software & pin-compatible with 40XX Processor Family
x Available in 179-pin PGA or 208-pin QFP
x Available at 80-200MHz, with mode bit dependent output
clock frequencies
x 64GB physical address space
x Processor family for a wide variety of embedded
applications
– LAN switches
– Routers
– Color printers
Description
The IDT79R4700 64-bit RISC Microprocessor is both software and
pin-compatible with the R4XXX processor family. With 64-bit processing
capabilities, the R4700 provides more computational power and data
movement bandwidth than is delivered to typical embedded systems by
32-bit processors.
The R4700 is upwardly software compatible with the IDT79R3000™
microprocessor family, including the IDTRISController™ 79R3051™,
R3052™, R3041™, R3081™ as well as the R4640™, R4650™, RC64474/
475™ and R5000™. An array of development tools facilitates rapid
development of R4700-based systems, allowing a variety of customers
access to the MIPS Open Architecture philosophy.
Block Diagram
Data Set A
Store Buffer
Data Tag A
DTLB Physical
Data Tag B
Instruction Set A
SysAD
Write Buffer
Read Buffer
Control
Data Set B
DBus
Floating-point
Register File
Unpacker/Packer
Floating-point
A d d /S u b /C v t/D iv /S q rt
Integer Divide
Floating-point/Integer
Multiply
Phase Lock Loop, Clocks
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Tag B
Instruction Select
Instruction Register
Instruction Set B
IBus
Tag AuxTag
Joint TLB
Load Aligner
Integer Register File
Integer/Address Adder
Coprocessor 0
Data TLB Virtual
D VA
Shifter/Store Aligner
Logic Unit
S y ste m /M e m o ry
Control
PC Incrementer
Branch Adder
Instruction TLB Virtual
IVA
Program Counter
The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-
marks of Integrated Device Technology, Inc.
2001 Integrated Device Technology, Inc.
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April 10, 2001
DSC 9096
1 page  
IDT79R4700
The RC4700 processor also supports a supervisor mode in which the
virtual address space is 256.5GB (2.5GB in 32-bit address mode),
divided into three regions that are based on the high-order bits of the
virtual address. If the RC4700 is configured for 64-bit virtual addressing,
the virtual address space layout is an upwardly compatible extension of
the 32-bit virtual address space layout. Figure 4 on page 5 shows the
wwawdd.dreastassshpeaect4eul.acyoomut for the 32-bit virtual address operation.
Memory Management Unit (MMU)
The Memory management unit controls the virtual memory system
page mapping. It consists of an instruction address translation buffer
(the ITLB), a data address translation buffer (the DTLB), a Joint TLB (the
JTLB), and co-processor registers used for the virtual memory mapping
sub-system.
Instruction TLB (ITLB)
The RC4700 also incorporates a two-entry instruction TLB. Each
entry maps a 4KB page. The instruction TLB improves performance by
allowing instruction address translation to occur in parallel with data
address translation. When a miss occurs on an instruction address
translation, the least-recently used ITLB entry is filled from the JTLB.
The operation of the ITLB is invisible to the user.
Data TLB (DTLB)
The RC4700 also incorporates a four-entry data TLB. Each entry
maps a 4KB page. The data TLB improves performance by allowing
data address translation to occur in parallel with instruction address
translation. When a miss occurs on a data address translation, the DTLB
is filled from the JTLB. The DTLB refill is pseudo-LRU: the least recently
used entry of the least recently used half is filled. The operation of the
DTLB is invisible to the user.
Joint TLB (JTLB)
For fast virtual-to-physical address decoding, the RC4700 uses a
large, fully associative TLB that maps 96 virtual pages to their corre-
sponding physical addresses. The TLB is organized as 48 pairs of even-
odd entries and maps a virtual address and address space identifier into
the large, 64GB physical address space.
Two mechanisms are provided to assist in controlling the amount of
mapped space and the replacement characteristics of various memory
regions. First, the page size can be configured, on a per-entry basis, to
map a page size of 4KB to 16MB (in multiples of 4). A CP0 register is
loaded with the page size of a mapping, and that size is entered into the
TLB when a new entry is written. Thus, operating systems can provide
special purpose maps; for example, a typical frame buffer can be
memory mapped using only one TLB entry.
The second mechanism controls the replacement algorithm, when a
TLB miss occurs. The RC4700 provides a random replacement algo-
rithm to select a TLB entry to be written with a new mapping; however,
the processor provides a mechanism whereby a system specific number
of mappings can be locked into the TLB and avoid being randomly
replaced. This facilitates the design of real-time systems, by allowing
deterministic access to critical software.
The joint TLB also contains information to control the cache coher-
ency protocol for each page. Specifically, each page has attribute bits to
determine whether the coherency algorithm is uncached, non-coherent
write-back, non-coherent write-through write-allocate or non-coherent
write-through no write-allocate. Non-coherent write-back is typically
used for both code and data on the RC4700; however, hardware-based
cache coherency is not supported.
0xFFFFFFFF
0xE0000000
0xDFFFFFFF
0xC0000000
0xBFFFFFFF
0xA0000000
0x9FFFFFFF
0x80000000
0x7FFFFFF
Kernel virtual address space
(kseg3)
Mapped, 0.5GB
Supervisor virtual address space
(sseg)
Mapped, 0.5GB
Uncached kernel physical address space
(kseg1)
Unmapped, 0.5GB
Cached kernel physical address space
(kseg0)
Unmapped, 0.5GB
User virtual address space
(useg)
Mapped, 2.0GB
0x00000000
Figure 4 Kernel Mode Virtual Addressing (32-bit Mode)
Cache Memory
To keep the RC4700’s high-performance pipeline full and operating
efficiently, the RC4700 incorporates on-chip instruction and data caches
that can be accessed in a single processor cycle. Each cache has its
own 64-bit data path and can be accessed in parallel.
Instruction Cache
The RC4700 incorporates a two-way set associative on-chip instruc-
tion cache. This virtually indexed, physically tagged cache is 16KB in
size and is protected with word parity.
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April 10, 2001
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IDT79R4700
Pin Description
The table below provides a list of interface, interrupt and miscellaneous pins that are available on the RC4700. Note that signals marked with an
asterisk are active when low. Boundary scan is not supported.
Pin Name Type
Description
System Interface
www.datasheet4u.com
ExtRqst*
I
External request
Signals that the system interface needs to submit an external request.
Release*
O Release interface
Signals that the processor is releasing the system interface to slave state.
RdRdy*
I Read Ready
Signals that an external agent can now accept a processor read.
WrRdy*
I Write Ready
Signals that an external agent can now accept a processor write request.
ValidIn*
I Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid com-
mand or data identifier on the SysCmd bus.
ValidOut*
O Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or
data identifier on the SysCmd bus.
SysAD(63:0)
I/O System address/data bus
A 64-bit address and data bus for communication between the processor and an external agent.
SysADC(7:0)
I/O System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.
SysCmd(8:0)
I/O System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an external agent.
SysCmdP
I/O Reserved system command/data identifier bus parity
for the R4700 unused on input and zero on output.
Clock/Control Interface
MasterClock
I Master clock
Master clock input at one half the processor operating frequency.
MasterOut
O Master clock out
Master clock output aligned with MasterClock.
RClock(1:0)
O Receive clocks
Two identical receive clocks at the system interface frequency.
TClock(1:0)
O Transmit clocks
Two identical transmit clocks at the system interface frequency.
IOOut
O Reserved for future output
Always HIGH.
IOIn I Reserved for future input
Should be driven HIGH.
SyncOut
O Synchronization clock out
Must be connected to SyncIn through an interconnect that models the interconnect between MasterOut,
TClock, RClock, and the external agent.
SyncIn
I Synchronization clock in
Synchronization clock input. See SyncOut.
Fault*
O Fault
Always HIGH.
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April 10, 2001
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